FR2876220B1 - Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees. - Google Patents

Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.

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Publication number
FR2876220B1
FR2876220B1 FR0452284A FR0452284A FR2876220B1 FR 2876220 B1 FR2876220 B1 FR 2876220B1 FR 0452284 A FR0452284 A FR 0452284A FR 0452284 A FR0452284 A FR 0452284A FR 2876220 B1 FR2876220 B1 FR 2876220B1
Authority
FR
France
Prior art keywords
electrical conduction
stacked structures
various insulating
vertical electrical
producing mixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR0452284A
Other languages
English (en)
Other versions
FR2876220A1 (fr
Inventor
Hubert Moriceau
Franck Fournel
Christophe Morales
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR0452284A priority Critical patent/FR2876220B1/fr
Priority to US11/576,743 priority patent/US7781300B2/en
Priority to PCT/IB2005/054432 priority patent/WO2006072871A2/fr
Priority to JP2007535322A priority patent/JP5329808B2/ja
Priority to EP05850920A priority patent/EP1797588A2/fr
Publication of FR2876220A1 publication Critical patent/FR2876220A1/fr
Application granted granted Critical
Publication of FR2876220B1 publication Critical patent/FR2876220B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
FR0452284A 2004-10-06 2004-10-06 Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees. Expired - Lifetime FR2876220B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR0452284A FR2876220B1 (fr) 2004-10-06 2004-10-06 Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.
US11/576,743 US7781300B2 (en) 2004-10-06 2005-10-06 Method for producing mixed stacked structures, different insulating areas and/or localised vertical electrical conducting areas
PCT/IB2005/054432 WO2006072871A2 (fr) 2004-10-06 2005-10-06 Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees
JP2007535322A JP5329808B2 (ja) 2004-10-06 2005-10-06 様々な絶縁領域及び／又は局所的な垂直導電領域を有する混合積層構造物を製造する方法
EP05850920A EP1797588A2 (fr) 2004-10-06 2005-10-06 Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0452284A FR2876220B1 (fr) 2004-10-06 2004-10-06 Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.

Publications (2)

Publication Number Publication Date
FR2876220A1 FR2876220A1 (fr) 2006-04-07
FR2876220B1 true FR2876220B1 (fr) 2007-09-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
FR0452284A Expired - Lifetime FR2876220B1 (fr) 2004-10-06 2004-10-06 Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.

Country Status (5)

Country Link
US (1) US7781300B2 (fr)
EP (1) EP1797588A2 (fr)
JP (1) JP5329808B2 (fr)
FR (1) FR2876220B1 (fr)
WO (1) WO2006072871A2 (fr)

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FR2932923B1 (fr) 2008-06-23 2011-03-25 Commissariat Energie Atomique Substrat heterogene comportant une couche sacrificielle et son procede de realisation.
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US9329336B2 (en) * 2012-07-06 2016-05-03 Micron Technology, Inc. Method of forming a hermetically sealed fiber to chip connection
KR102007258B1 (ko) * 2012-11-21 2019-08-05 삼성전자주식회사 광전 집적회로 기판의 제조방법
FR3008190B1 (fr) 2013-07-08 2015-08-07 Commissariat Energie Atomique Procede et dispositif de mesure d'un champ magnetique au moyen d'excitations synchronisees
CN104752311B (zh) * 2013-12-27 2018-02-06 中芯国际集成电路制造(上海)有限公司 一种绝缘体上硅衬底及其制造方法
FR3039699B1 (fr) * 2015-07-31 2017-07-28 Commissariat Energie Atomique Procede de realisation d'un dispositif electronique
FR3040108B1 (fr) 2015-08-12 2017-08-11 Commissariat Energie Atomique Procede de fabrication d'une structure semi-conductrice avec collage direct temporaire exploitant une couche poreuse
CN120652751B (zh) * 2025-06-10 2026-01-02 广州市艾佛光通科技有限公司 一种降低减薄崩边率的晶圆键合封装方法及半导体器件

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Also Published As

Publication number Publication date
JP2008516443A (ja) 2008-05-15
EP1797588A2 (fr) 2007-06-20
US7781300B2 (en) 2010-08-24
FR2876220A1 (fr) 2006-04-07
WO2006072871A2 (fr) 2006-07-13
WO2006072871A3 (fr) 2006-11-30
JP5329808B2 (ja) 2013-10-30
US20070202660A1 (en) 2007-08-30

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