ATE417318T1 - Elektronische datenverarbeitungsschaltung, die gepackte wörter über einen bus sendet - Google Patents

Elektronische datenverarbeitungsschaltung, die gepackte wörter über einen bus sendet

Info

Publication number
ATE417318T1
ATE417318T1 AT04770365T AT04770365T ATE417318T1 AT E417318 T1 ATE417318 T1 AT E417318T1 AT 04770365 T AT04770365 T AT 04770365T AT 04770365 T AT04770365 T AT 04770365T AT E417318 T1 ATE417318 T1 AT E417318T1
Authority
AT
Austria
Prior art keywords
bus
data
handling units
processing circuit
words
Prior art date
Application number
AT04770365T
Other languages
English (en)
Inventor
Milind Kulkarni
Bijo Thomas
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE417318T1 publication Critical patent/ATE417318T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1678—Details of memory controller using bus width
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
AT04770365T 2003-11-13 2004-11-03 Elektronische datenverarbeitungsschaltung, die gepackte wörter über einen bus sendet ATE417318T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03104176 2003-11-13

Publications (1)

Publication Number Publication Date
ATE417318T1 true ATE417318T1 (de) 2008-12-15

Family

ID=34585891

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04770365T ATE417318T1 (de) 2003-11-13 2004-11-03 Elektronische datenverarbeitungsschaltung, die gepackte wörter über einen bus sendet

Country Status (8)

Country Link
US (1) US7480756B2 (de)
EP (1) EP1685495B1 (de)
JP (1) JP4621686B2 (de)
KR (1) KR101034514B1 (de)
CN (1) CN100547569C (de)
AT (1) ATE417318T1 (de)
DE (1) DE602004018371D1 (de)
WO (1) WO2005048115A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4982871B2 (ja) * 2005-02-07 2012-07-25 エスティー‐エリクソン、ソシエテ、アノニム データ処理システムおよびキャッシュ取り替え方法
US7765350B2 (en) 2005-09-14 2010-07-27 Koninklijke Philips Electronics N.V. Method and system for bus arbitration
US7610417B2 (en) * 2005-11-30 2009-10-27 Rambus Inc. Data-width translator coupled between variable-width and fixed-width data ports and supporting multiple data-width configurations
US10394735B2 (en) * 2017-01-09 2019-08-27 Nanya Technology Corporation Comparative forwarding circuit providing first datum and second datum to one of first circuit and second circuit according to target address
CN114579491A (zh) * 2022-01-28 2022-06-03 新华三技术有限公司合肥分公司 一种集成电路总线复用装置以及网络设备

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4447878A (en) * 1978-05-30 1984-05-08 Intel Corporation Apparatus and method for providing byte and word compatible information transfers
JPS5727330A (en) * 1980-07-25 1982-02-13 Hitachi Ltd Process control device
US4667305A (en) * 1982-06-30 1987-05-19 International Business Machines Corporation Circuits for accessing a variable width data bus with a variable width data field
US4841435A (en) * 1986-10-29 1989-06-20 Saxpy Computer Corporation Data alignment system for random and block transfers of embedded subarrays of an array onto a system bus
US4878166A (en) * 1987-12-15 1989-10-31 Advanced Micro Devices, Inc. Direct memory access apparatus and methods for transferring data between buses having different performance characteristics
DE68926043T2 (de) * 1989-07-20 1996-08-22 Toshiba Kawasaki Kk Mehrprozessor-Computersystem
CA2045756C (en) 1990-06-29 1996-08-20 Gregg Bouchard Combined queue for invalidates and return data in multiprocessor system
US5388227A (en) * 1990-08-14 1995-02-07 Nexgen Microsystems Transparent data bus sizing
JPH04225458A (ja) * 1990-12-27 1992-08-14 Nec Eng Ltd コンピュータ
JPH06161620A (ja) * 1992-11-20 1994-06-10 Hitachi Ltd 出力同時変化制御方式
US5561772A (en) * 1993-02-10 1996-10-01 Elonex Technologies, Inc. Expansion bus system for replicating an internal bus as an external bus with logical interrupts replacing physical interrupt lines
US5561780A (en) * 1993-12-30 1996-10-01 Intel Corporation Method and apparatus for combining uncacheable write data into cache-line-sized write buffers
US5790874A (en) * 1994-09-30 1998-08-04 Kabushiki Kaisha Toshiba Information processing apparatus for reducing power consumption by minimizing hamming distance between consecutive instruction
WO1997011420A1 (en) * 1995-09-18 1997-03-27 Hitachi, Ltd. Bus control method, and bus control circuit and data processor using the bus control method
JPH10177543A (ja) * 1996-12-18 1998-06-30 Matsushita Electric Ind Co Ltd バス制御回路
US5901294A (en) 1997-09-18 1999-05-04 International Business Machines Corporation Method and system for bus arbitration in a multiprocessor system utilizing simultaneous variable-width bus access
JPH11259417A (ja) * 1998-03-13 1999-09-24 Fujitsu Ltd バスアクセス方式およびバスアクセス制御装置
US6122715A (en) * 1998-03-31 2000-09-19 Intel Corporation Method and system for optimizing write combining performance in a shared buffer structure
US6618777B1 (en) * 1999-01-21 2003-09-09 Analog Devices, Inc. Method and apparatus for communicating between multiple functional units in a computer environment
US6366984B1 (en) * 1999-05-11 2002-04-02 Intel Corporation Write combining buffer that supports snoop request
US7085875B1 (en) * 2000-04-06 2006-08-01 Avaya Communication Israel Ltd. Modular switch with dynamic bus
GB2375695B (en) * 2001-05-19 2004-08-25 At & T Lab Cambridge Ltd Improved power efficency in microprocessors
US7257661B2 (en) * 2001-09-21 2007-08-14 Nxp B.V. Scalable home control platform and architecture

Also Published As

Publication number Publication date
KR101034514B1 (ko) 2011-05-17
EP1685495A2 (de) 2006-08-02
US20070083693A1 (en) 2007-04-12
CN100547569C (zh) 2009-10-07
WO2005048115A3 (en) 2005-07-14
KR20070007763A (ko) 2007-01-16
US7480756B2 (en) 2009-01-20
DE602004018371D1 (de) 2009-01-22
EP1685495B1 (de) 2008-12-10
JP4621686B2 (ja) 2011-01-26
JP2007511828A (ja) 2007-05-10
CN1879095A (zh) 2006-12-13
WO2005048115A2 (en) 2005-05-26

Similar Documents

Publication Publication Date Title
TW200502851A (en) Microprocessor including a first level cache and a second level cache having different cache line sizes
US10789177B2 (en) Multiple memory type memory module systems and methods
ATE366985T1 (de) Integrierte schaltung und verfahren zum cache- umabbilden
JP2016526748A5 (de)
US20150278017A1 (en) Memory module having error correction logic
TW200710655A (en) Memory module, memory system, and information device
ATE339006T1 (de) Pufferanordnung für speicher
TW200502756A (en) Memory device
TW200733127A (en) Data output driving circuit of semiconductor memory apparatus
ATE267420T1 (de) Sram-steuerungvorrichtung für parallele prozessorarchitektur mit adressen- und befehlswarteschlange und arbiter
ATE554443T1 (de) Anweisungsgesteuerte datenverarbeitungseinrichtung und -verfahren
DE60316190D1 (de) Speichersystem mit speichermodulen und mehrerer speicherbänke
ATE372542T1 (de) Zugriff zum breiten speicher
KR20160050158A (ko) 스캔 센스 드라이버 및 이를 포함하는 디스플레이 장치
US10162750B2 (en) System address reconstruction
WO2019067929A1 (en) MULTIPLE CRITERIA POWER MANAGEMENT SYSTEM WITH ACCROGRESSED ACCELERATOR ARCHITECTURES
ATE417318T1 (de) Elektronische datenverarbeitungsschaltung, die gepackte wörter über einen bus sendet
JP2017517067A5 (de)
GB2436505A (en) A single chip having a magnetoresistive memory
TW200519604A (en) Prefetch control in a data processing system
WO2008019274A3 (en) Method and apparatus for reducing power consumption in a content addressable memory
KR20130002564A (ko) 반도체 모듈 및 이를 포함하는 테스트 시스템
TW200735099A (en) Semiconductor memory, memory system, and operation method of semiconductor memory
CN111123818B (zh) 一种plc浮点数和定点数相互转换控制系统及方法
TW200643724A (en) System for improving bandwidth among a plurality of memory controllers and method thereof

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties