ATE430961T1 - Verfahren und vorrichtung zur transaktionsarbitrierung zwischen rechnersystembereichen - Google Patents

Verfahren und vorrichtung zur transaktionsarbitrierung zwischen rechnersystembereichen

Info

Publication number
ATE430961T1
ATE430961T1 AT02789370T AT02789370T ATE430961T1 AT E430961 T1 ATE430961 T1 AT E430961T1 AT 02789370 T AT02789370 T AT 02789370T AT 02789370 T AT02789370 T AT 02789370T AT E430961 T1 ATE430961 T1 AT E430961T1
Authority
AT
Austria
Prior art keywords
transaction
error
domains
portions
devices
Prior art date
Application number
AT02789370T
Other languages
English (en)
Inventor
Andrew Phelps
Wormer Thomas Van
Gary Riddle
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of ATE430961T1 publication Critical patent/ATE430961T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Detection And Correction Of Errors (AREA)
  • Debugging And Monitoring (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
AT02789370T 2001-11-01 2002-11-01 Verfahren und vorrichtung zur transaktionsarbitrierung zwischen rechnersystembereichen ATE430961T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/034,919 US6915450B2 (en) 2001-11-01 2001-11-01 Method and apparatus for arbitrating transactions between domains in a computer system
PCT/US2002/035097 WO2003038619A1 (en) 2001-11-01 2002-11-01 Method and apparatus for arbitrating transactions between domains in a computer system

Publications (1)

Publication Number Publication Date
ATE430961T1 true ATE430961T1 (de) 2009-05-15

Family

ID=21879459

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02789370T ATE430961T1 (de) 2001-11-01 2002-11-01 Verfahren und vorrichtung zur transaktionsarbitrierung zwischen rechnersystembereichen

Country Status (6)

Country Link
US (1) US6915450B2 (de)
EP (1) EP1377905B1 (de)
JP (1) JP2005508045A (de)
AT (1) ATE430961T1 (de)
DE (1) DE60232233D1 (de)
WO (1) WO2003038619A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7346825B2 (en) * 2001-09-06 2008-03-18 Intel Corporation Error method, system and medium
US6901531B2 (en) * 2001-11-30 2005-05-31 Sun Microsystems, Inc. Automatic system control failover
US7454552B2 (en) * 2003-11-18 2008-11-18 Topside Research, Llc Switch with transparent and non-transparent ports
US7421532B2 (en) * 2003-11-18 2008-09-02 Topside Research, Llc Switching with transparent and non-transparent ports
JP2006260140A (ja) * 2005-03-17 2006-09-28 Fujitsu Ltd データ処理システム
JP5136550B2 (ja) * 2007-06-01 2013-02-06 富士通株式会社 情報処理装置及び情報処理装置の再構成方法
US9727625B2 (en) * 2014-01-16 2017-08-08 International Business Machines Corporation Parallel transaction messages for database replication
US20170070397A1 (en) * 2015-09-09 2017-03-09 Ca, Inc. Proactive infrastructure fault, root cause, and impact management

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5084816A (en) * 1987-11-25 1992-01-28 Bell Communications Research, Inc. Real time fault tolerant transaction processing system
US5392291A (en) 1991-05-20 1995-02-21 Alliedsignal Inc. Fault-tolerant CITO communication system
JPH05191388A (ja) 1992-01-14 1993-07-30 Fujitsu Ltd 通信処理システム
US5457683A (en) * 1993-05-07 1995-10-10 Apple Computer, Inc. Link and discovery protocols for a ring interconnect architecture
US5440538A (en) 1993-09-23 1995-08-08 Massachusetts Institute Of Technology Communication system with redundant links and data bit time multiplexing
US5509125A (en) * 1993-09-29 1996-04-16 Silicon Graphics, Inc. System and method for fair arbitration on a multi-domain multiprocessor bus
JP3172387B2 (ja) 1994-06-01 2001-06-04 インターナショナル・ビジネス・マシーンズ・コーポレ−ション 入出力通信サブシステム及び方法
US5781449A (en) * 1995-08-10 1998-07-14 Advanced System Technologies, Inc. Response time measurement apparatus and method
US5761445A (en) * 1996-04-26 1998-06-02 Unisys Corporation Dual domain data processing network with cross-linking data queues and selective priority arbitration logic
US5931938A (en) 1996-12-12 1999-08-03 Sun Microsystems, Inc. Multiprocessor computer having configurable hardware system domains
US6161160A (en) * 1998-09-03 2000-12-12 Advanced Micro Devices, Inc. Network interface device architecture for storing transmit and receive data in a random access buffer memory across independent clock domains
US6889343B2 (en) * 2001-03-19 2005-05-03 Sun Microsystems, Inc. Method and apparatus for verifying consistency between a first address repeater and a second address repeater
US6898728B2 (en) * 2001-09-25 2005-05-24 Sun Microsystems, Inc. System domain targeted, configurable interconnection

Also Published As

Publication number Publication date
US20030084373A1 (en) 2003-05-01
US6915450B2 (en) 2005-07-05
JP2005508045A (ja) 2005-03-24
WO2003038619A1 (en) 2003-05-08
EP1377905A1 (de) 2004-01-07
EP1377905B1 (de) 2009-05-06
DE60232233D1 (de) 2009-06-18

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