ATE417321T1 - Vermittlungs-/netzwerkadapterport für geclusterte computer mit einer kette von mehrfach adaptiven prozessoren in einem dual-inline- speichermodulformat - Google Patents
Vermittlungs-/netzwerkadapterport für geclusterte computer mit einer kette von mehrfach adaptiven prozessoren in einem dual-inline- speichermodulformatInfo
- Publication number
- ATE417321T1 ATE417321T1 AT02794847T AT02794847T ATE417321T1 AT E417321 T1 ATE417321 T1 AT E417321T1 AT 02794847 T AT02794847 T AT 02794847T AT 02794847 T AT02794847 T AT 02794847T AT E417321 T1 ATE417321 T1 AT E417321T1
- Authority
- AT
- Austria
- Prior art keywords
- memory module
- network adapter
- adapter port
- chain
- switching
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/932,330 US7373440B2 (en) | 1997-12-17 | 2001-08-17 | Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE417321T1 true ATE417321T1 (de) | 2008-12-15 |
Family
ID=25462158
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT02794847T ATE417321T1 (de) | 2001-08-17 | 2002-05-06 | Vermittlungs-/netzwerkadapterport für geclusterte computer mit einer kette von mehrfach adaptiven prozessoren in einem dual-inline- speichermodulformat |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US7373440B2 (de) |
| EP (1) | EP1442378B1 (de) |
| JP (1) | JP4128956B2 (de) |
| AT (1) | ATE417321T1 (de) |
| CA (1) | CA2456179A1 (de) |
| DE (1) | DE60230309D1 (de) |
| WO (1) | WO2003017118A1 (de) |
Families Citing this family (48)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040236877A1 (en) * | 1997-12-17 | 2004-11-25 | Lee A. Burton | Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM) |
| US7197575B2 (en) * | 1997-12-17 | 2007-03-27 | Src Computers, Inc. | Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers |
| US7464295B2 (en) * | 2002-10-11 | 2008-12-09 | Broadcom Corporation | Software programmable verification tool having multiple built-in self-test (BIST) modules for testing and debugging multiple devices under test (DUT) |
| US8108564B2 (en) | 2003-10-30 | 2012-01-31 | International Business Machines Corporation | System and method for a configurable interface controller |
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| US7356737B2 (en) | 2004-10-29 | 2008-04-08 | International Business Machines Corporation | System, method and storage medium for testing a memory module |
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| US7395476B2 (en) | 2004-10-29 | 2008-07-01 | International Business Machines Corporation | System, method and storage medium for providing a high speed test interface to a memory subsystem |
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| US8984256B2 (en) * | 2006-02-03 | 2015-03-17 | Russell Fish | Thread optimized multiprocessor architecture |
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| US7594055B2 (en) | 2006-05-24 | 2009-09-22 | International Business Machines Corporation | Systems and methods for providing distributed technology independent memory controllers |
| US7640386B2 (en) * | 2006-05-24 | 2009-12-29 | International Business Machines Corporation | Systems and methods for providing memory modules with multiple hub devices |
| US7584336B2 (en) | 2006-06-08 | 2009-09-01 | International Business Machines Corporation | Systems and methods for providing data modification operations in memory subsystems |
| US7493439B2 (en) * | 2006-08-01 | 2009-02-17 | International Business Machines Corporation | Systems and methods for providing performance monitoring in a memory system |
| US7669086B2 (en) * | 2006-08-02 | 2010-02-23 | International Business Machines Corporation | Systems and methods for providing collision detection in a memory system |
| US7581073B2 (en) | 2006-08-09 | 2009-08-25 | International Business Machines Corporation | Systems and methods for providing distributed autonomous power management in a memory system |
| US7587559B2 (en) * | 2006-08-10 | 2009-09-08 | International Business Machines Corporation | Systems and methods for memory module power management |
| US7539842B2 (en) | 2006-08-15 | 2009-05-26 | International Business Machines Corporation | Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tables |
| US7490217B2 (en) | 2006-08-15 | 2009-02-10 | International Business Machines Corporation | Design structure for selecting memory busses according to physical memory organization information stored in virtual address translation tables |
| US7477522B2 (en) | 2006-10-23 | 2009-01-13 | International Business Machines Corporation | High density high reliability memory module with a fault tolerant address and command bus |
| US7870459B2 (en) * | 2006-10-23 | 2011-01-11 | International Business Machines Corporation | High density high reliability memory module with power gating and a fault tolerant address and command bus |
| US7721140B2 (en) * | 2007-01-02 | 2010-05-18 | International Business Machines Corporation | Systems and methods for improving serviceability of a memory system |
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| EP2366144B1 (de) * | 2008-10-15 | 2015-09-30 | Hyperion Core, Inc. | Sequentieller prozessor mit einem alu-array |
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-
2001
- 2001-08-17 US US09/932,330 patent/US7373440B2/en not_active Expired - Fee Related
-
2002
- 2002-05-06 AT AT02794847T patent/ATE417321T1/de not_active IP Right Cessation
- 2002-05-06 CA CA002456179A patent/CA2456179A1/en not_active Abandoned
- 2002-05-06 JP JP2003521956A patent/JP4128956B2/ja not_active Expired - Fee Related
- 2002-05-06 DE DE60230309T patent/DE60230309D1/de not_active Expired - Fee Related
- 2002-05-06 EP EP02794847A patent/EP1442378B1/de not_active Expired - Lifetime
- 2002-05-06 WO PCT/US2002/014574 patent/WO2003017118A1/en not_active Ceased
-
2004
- 2004-11-23 US US10/996,016 patent/US7421524B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2005500621A (ja) | 2005-01-06 |
| EP1442378A4 (de) | 2006-05-24 |
| US7373440B2 (en) | 2008-05-13 |
| EP1442378A1 (de) | 2004-08-04 |
| EP1442378B1 (de) | 2008-12-10 |
| US20050091434A1 (en) | 2005-04-28 |
| US20020019926A1 (en) | 2002-02-14 |
| JP4128956B2 (ja) | 2008-07-30 |
| DE60230309D1 (de) | 2009-01-22 |
| WO2003017118A1 (en) | 2003-02-27 |
| US7421524B2 (en) | 2008-09-02 |
| CA2456179A1 (en) | 2003-02-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |