ATE43204T1 - Verfahren zum herstellen von integrierten schaltungen durch mos- und cmos-technologie und entsprechende cmos-struktur. - Google Patents

Verfahren zum herstellen von integrierten schaltungen durch mos- und cmos-technologie und entsprechende cmos-struktur.

Info

Publication number
ATE43204T1
ATE43204T1 AT86400403T AT86400403T ATE43204T1 AT E43204 T1 ATE43204 T1 AT E43204T1 AT 86400403 T AT86400403 T AT 86400403T AT 86400403 T AT86400403 T AT 86400403T AT E43204 T1 ATE43204 T1 AT E43204T1
Authority
AT
Austria
Prior art keywords
silicide
gate
source
drain
photogravure
Prior art date
Application number
AT86400403T
Other languages
English (en)
Inventor
Agustin Monroy
Danielle Prudhomme
Michel Marty
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Application granted granted Critical
Publication of ATE43204T1 publication Critical patent/ATE43204T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
AT86400403T 1985-02-26 1986-02-25 Verfahren zum herstellen von integrierten schaltungen durch mos- und cmos-technologie und entsprechende cmos-struktur. ATE43204T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8502769A FR2578097A1 (fr) 1985-02-26 1985-02-26 Procede de fabrication de circuits integres en technologie mos et cmos et structure cmos correspondante
EP86400403A EP0194916B1 (de) 1985-02-26 1986-02-25 Verfahren zum Herstellen von integrierten Schaltungen durch MOS- und CMOS-Technologie und entsprechende CMOS-Struktur

Publications (1)

Publication Number Publication Date
ATE43204T1 true ATE43204T1 (de) 1989-06-15

Family

ID=9316638

Family Applications (1)

Application Number Title Priority Date Filing Date
AT86400403T ATE43204T1 (de) 1985-02-26 1986-02-25 Verfahren zum herstellen von integrierten schaltungen durch mos- und cmos-technologie und entsprechende cmos-struktur.

Country Status (4)

Country Link
EP (1) EP0194916B1 (de)
AT (1) ATE43204T1 (de)
DE (1) DE3663427D1 (de)
FR (1) FR2578097A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11489058B2 (en) 2018-07-27 2022-11-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and associated manufacturing method

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4295897B1 (en) * 1979-10-03 1997-09-09 Texas Instruments Inc Method of making cmos integrated circuit device
US4280271A (en) * 1979-10-11 1981-07-28 Texas Instruments Incorporated Three level interconnect process for manufacture of integrated circuit devices
EP0054259B1 (de) * 1980-12-12 1986-08-06 Kabushiki Kaisha Toshiba Verfahren zur Herstellung einer Halbleiteranordnung vom MIS-Typ
DE3132809A1 (de) * 1981-08-19 1983-03-10 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von integrierten mos-feldeffekttransistoren, insbesondere von komplementaeren mos-feldeffekttransistorenschaltungen mit einer aus metallsiliziden bestehenden zusaetzlichen leiterbahnebene
DE3230077A1 (de) * 1982-08-12 1984-02-16 Siemens AG, 1000 Berlin und 8000 München Integrierte bipolar- und mos-transistoren enthaltende halbleiterschaltung auf einem chip und verfahren zu ihrer herstellung
US4477310A (en) * 1983-08-12 1984-10-16 Tektronix, Inc. Process for manufacturing MOS integrated circuit with improved method of forming refractory metal silicide areas
DE3330851A1 (de) * 1983-08-26 1985-03-14 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen

Also Published As

Publication number Publication date
EP0194916A1 (de) 1986-09-17
DE3663427D1 (en) 1989-06-22
FR2578097A1 (fr) 1986-08-29
EP0194916B1 (de) 1989-05-17

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee