ATE441206T1 - Verfahren zum erhalten einer dünnen schicht mit einer geringen dichte von líchern - Google Patents
Verfahren zum erhalten einer dünnen schicht mit einer geringen dichte von líchernInfo
- Publication number
- ATE441206T1 ATE441206T1 AT04806549T AT04806549T ATE441206T1 AT E441206 T1 ATE441206 T1 AT E441206T1 AT 04806549 T AT04806549 T AT 04806549T AT 04806549 T AT04806549 T AT 04806549T AT E441206 T1 ATE441206 T1 AT E441206T1
- Authority
- AT
- Austria
- Prior art keywords
- holes
- layer
- obtaining
- thin layer
- low density
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Landscapes
- Thin Film Transistor (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Formation Of Insulating Films (AREA)
- Superconductors And Manufacturing Methods Therefor (AREA)
- Separation Using Semi-Permeable Membranes (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/IB2004/004390 WO2006070220A1 (en) | 2004-12-28 | 2004-12-28 | Method for obtaining a thin layer having a low density of holes |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE441206T1 true ATE441206T1 (de) | 2009-09-15 |
Family
ID=34960268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT04806549T ATE441206T1 (de) | 2004-12-28 | 2004-12-28 | Verfahren zum erhalten einer dünnen schicht mit einer geringen dichte von líchern |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7485545B2 (de) |
| EP (1) | EP1831922B9 (de) |
| JP (1) | JP2008526010A (de) |
| CN (1) | CN100550342C (de) |
| AT (1) | ATE441206T1 (de) |
| DE (1) | DE602004022882D1 (de) |
| WO (1) | WO2006070220A1 (de) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2903809B1 (fr) | 2006-07-13 | 2008-10-17 | Soitec Silicon On Insulator | Traitement thermique de stabilisation d'interface e collage. |
| JP5135935B2 (ja) * | 2007-07-27 | 2013-02-06 | 信越半導体株式会社 | 貼り合わせウエーハの製造方法 |
| EP2161741B1 (de) * | 2008-09-03 | 2014-06-11 | Soitec | Verfahren zur Herstellung eines Halbleiters auf einem Isoliersubstrat mit verringerter SECCO-Fehlerdichte |
| FR2943458B1 (fr) | 2009-03-18 | 2011-06-10 | Soitec Silicon On Insulator | Procede de finition d'un substrat de type "silicium sur isolant" soi |
| JP5703920B2 (ja) * | 2011-04-13 | 2015-04-22 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
| JP2013143407A (ja) | 2012-01-06 | 2013-07-22 | Shin Etsu Handotai Co Ltd | 貼り合わせｓｏｉウェーハの製造方法 |
| JP5673572B2 (ja) | 2012-01-24 | 2015-02-18 | 信越半導体株式会社 | 貼り合わせｓｏｉウェーハの製造方法 |
| JP2016082093A (ja) * | 2014-10-17 | 2016-05-16 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
Family Cites Families (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
| JPH1084100A (ja) * | 1996-09-06 | 1998-03-31 | Shin Etsu Handotai Co Ltd | Ｓｏｉ基板の製造方法 |
| EP0849788B1 (de) | 1996-12-18 | 2004-03-10 | Canon Kabushiki Kaisha | Vefahren zum Herstellen eines Halbleiterartikels unter Verwendung eines Substrates mit einer porösen Halbleiterschicht |
| US6146979A (en) | 1997-05-12 | 2000-11-14 | Silicon Genesis Corporation | Pressurized microbubble thin film separation process using a reusable substrate |
| FR2777115B1 (fr) * | 1998-04-07 | 2001-07-13 | Commissariat Energie Atomique | Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede |
| JPH11307472A (ja) * | 1998-04-23 | 1999-11-05 | Shin Etsu Handotai Co Ltd | 水素イオン剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ |
| FR2797714B1 (fr) * | 1999-08-20 | 2001-10-26 | Soitec Silicon On Insulator | Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede |
| FR2797713B1 (fr) * | 1999-08-20 | 2002-08-02 | Soitec Silicon On Insulator | Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede |
| JP2002110688A (ja) | 2000-09-29 | 2002-04-12 | Canon Inc | Ｓｏｉの熱処理方法及び製造方法 |
| FR2894990B1 (fr) * | 2005-12-21 | 2008-02-22 | Soitec Silicon On Insulator | Procede de fabrication de substrats, notamment pour l'optique,l'electronique ou l'optoelectronique et substrat obtenu selon ledit procede |
| JP4304879B2 (ja) * | 2001-04-06 | 2009-07-29 | 信越半導体株式会社 | 水素イオンまたは希ガスイオンの注入量の決定方法 |
| JP2004533125A (ja) * | 2001-06-22 | 2004-10-28 | エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド | イオン注入によるイントリンシックゲッタリングを有するシリコン・オン・インシュレータ構造体を製造する方法 |
| FR2827423B1 (fr) * | 2001-07-16 | 2005-05-20 | Soitec Silicon On Insulator | Procede d'amelioration d'etat de surface |
| JPWO2003046993A1 (ja) | 2001-11-29 | 2005-04-14 | 信越半導体株式会社 | Ｓｏｉウェーハの製造方法 |
| FR2846786B1 (fr) | 2002-11-05 | 2005-06-17 | Procede de recuit thermique rapide de tranches a couronne | |
| JP2004259970A (ja) | 2003-02-26 | 2004-09-16 | Shin Etsu Handotai Co Ltd | Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ |
| FR2852143B1 (fr) | 2003-03-04 | 2005-10-14 | Soitec Silicon On Insulator | Procede de traitement preventif de la couronne d'une tranche multicouche |
| FR2855908B1 (fr) | 2003-06-06 | 2005-08-26 | Soitec Silicon On Insulator | Procede d'obtention d'une structure comprenant au moins un substrat et une couche ultramince |
| EP1652230A2 (de) | 2003-07-29 | 2006-05-03 | S.O.I.Tec Silicon on Insulator Technologies | Verfahren zum erhalten einer qualitativ hochwertigen dünnschicht durch coimplantation und thermisches ausheizen |
| FR2858461B1 (fr) * | 2003-07-30 | 2005-11-04 | Soitec Silicon On Insulator | Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques |
| FR2860249B1 (fr) * | 2003-09-30 | 2005-12-09 | Michel Bruel | Procede de fabrication d'une structure en forme de plaque, en particulier en silicium, application de procede, et structure en forme de plaque, en particulier en silicium |
| FR2861497B1 (fr) | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | Procede de transfert catastrophique d'une couche fine apres co-implantation |
| US7772087B2 (en) | 2003-12-19 | 2010-08-10 | Commissariat A L'energie Atomique | Method of catastrophic transfer of a thin film after co-implantation |
-
2004
- 2004-12-28 EP EP04806549A patent/EP1831922B9/de not_active Expired - Lifetime
- 2004-12-28 CN CNB2004800447452A patent/CN100550342C/zh not_active Expired - Lifetime
- 2004-12-28 JP JP2007547685A patent/JP2008526010A/ja active Pending
- 2004-12-28 WO PCT/IB2004/004390 patent/WO2006070220A1/en not_active Ceased
- 2004-12-28 DE DE602004022882T patent/DE602004022882D1/de not_active Expired - Lifetime
- 2004-12-28 AT AT04806549T patent/ATE441206T1/de not_active IP Right Cessation
-
2006
- 2006-01-10 US US11/328,061 patent/US7485545B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20060141755A1 (en) | 2006-06-29 |
| DE602004022882D1 (de) | 2009-10-08 |
| EP1831922B9 (de) | 2010-02-24 |
| CN101091242A (zh) | 2007-12-19 |
| EP1831922A1 (de) | 2007-09-12 |
| CN100550342C (zh) | 2009-10-14 |
| US7485545B2 (en) | 2009-02-03 |
| WO2006070220A1 (en) | 2006-07-06 |
| EP1831922B1 (de) | 2009-08-26 |
| JP2008526010A (ja) | 2008-07-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |