ATE442667T1 - Transfer einer dünnschicht von einem wafer mit einer pufferschicht - Google Patents

Transfer einer dünnschicht von einem wafer mit einer pufferschicht

Info

Publication number
ATE442667T1
ATE442667T1 AT03762848T AT03762848T ATE442667T1 AT E442667 T1 ATE442667 T1 AT E442667T1 AT 03762848 T AT03762848 T AT 03762848T AT 03762848 T AT03762848 T AT 03762848T AT E442667 T1 ATE442667 T1 AT E442667T1
Authority
AT
Austria
Prior art keywords
layer
lattice parameter
wafer
buffer layer
semiconductor material
Prior art date
Application number
AT03762848T
Other languages
English (en)
Inventor
Bruno Ghyselen
Cecile Aulnette
Benedite Osternaud
Nicolas Daval
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE442667T1 publication Critical patent/ATE442667T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1924—Preparing SOI wafers with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Recrystallisation Techniques (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Element Separation (AREA)
  • Magnetic Record Carriers (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Storage Of Web-Like Or Filamentary Materials (AREA)
  • Laminated Bodies (AREA)
AT03762848T 2002-07-09 2003-07-09 Transfer einer dünnschicht von einem wafer mit einer pufferschicht ATE442667T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0208600A FR2842349B1 (fr) 2002-07-09 2002-07-09 Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon
PCT/IB2003/003466 WO2004006327A2 (en) 2002-07-09 2003-07-09 Transfer of a thin layer from a wafer comprising a buffer layer

Publications (1)

Publication Number Publication Date
ATE442667T1 true ATE442667T1 (de) 2009-09-15

Family

ID=29763664

Family Applications (2)

Application Number Title Priority Date Filing Date
AT03762848T ATE442667T1 (de) 2002-07-09 2003-07-09 Transfer einer dünnschicht von einem wafer mit einer pufferschicht
AT03762850T ATE443344T1 (de) 2002-07-09 2003-07-09 Übertragung einer dünnen schicht von einer scheibe mit einer pufferschicht

Family Applications After (1)

Application Number Title Priority Date Filing Date
AT03762850T ATE443344T1 (de) 2002-07-09 2003-07-09 Übertragung einer dünnen schicht von einer scheibe mit einer pufferschicht

Country Status (11)

Country Link
US (1) US6991956B2 (de)
EP (2) EP1522097B9 (de)
JP (2) JP4904478B2 (de)
KR (1) KR100796832B1 (de)
CN (1) CN100477150C (de)
AT (2) ATE442667T1 (de)
AU (2) AU2003249475A1 (de)
DE (2) DE60329192D1 (de)
FR (1) FR2842349B1 (de)
TW (1) TWI289900B (de)
WO (2) WO2004006311A2 (de)

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FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
US7227176B2 (en) 1998-04-10 2007-06-05 Massachusetts Institute Of Technology Etch stop layer system
EP1309989B1 (de) 2000-08-16 2007-01-10 Massachusetts Institute Of Technology Verfahren für die herstellung eines halbleiterartikels mittels graduellem epitaktischen wachsen
US6649480B2 (en) 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6830976B2 (en) 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6703688B1 (en) 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
WO2002082514A1 (en) 2001-04-04 2002-10-17 Massachusetts Institute Of Technology A method for semiconductor device fabrication
US6717213B2 (en) * 2001-06-29 2004-04-06 Intel Corporation Creation of high mobility channels in thin-body SOI devices
US7074623B2 (en) 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US7335545B2 (en) 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US7615829B2 (en) 2002-06-07 2009-11-10 Amberwave Systems Corporation Elevated source and drain elements for strained-channel heterojuntion field-effect transistors
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7307273B2 (en) 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US6946371B2 (en) 2002-06-10 2005-09-20 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
US6982474B2 (en) 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
US7018910B2 (en) * 2002-07-09 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Transfer of a thin layer from a wafer comprising a buffer layer
US7510949B2 (en) 2002-07-09 2009-03-31 S.O.I.Tec Silicon On Insulator Technologies Methods for producing a multilayer semiconductor structure
US6953736B2 (en) 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
WO2004019403A2 (en) * 2002-08-26 2004-03-04 S.O.I.Tec Silicon On Insulator Technologies Mechanical recycling of a wafer comprising a buffer layer, after having taken a layer therefrom
WO2004019404A2 (en) * 2002-08-26 2004-03-04 S.O.I.Tec Silicon On Insulator Technologies Recycling a wafer comprising a buffer layer, after having taken off a thin layer therefrom
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US7332417B2 (en) 2003-01-27 2008-02-19 Amberwave Systems Corporation Semiconductor structures with structural homogeneity
US6960781B2 (en) 2003-03-07 2005-11-01 Amberwave Systems Corporation Shallow trench isolation process
FR2861497B1 (fr) * 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
FR2867307B1 (fr) 2004-03-05 2006-05-26 Soitec Silicon On Insulator Traitement thermique apres detachement smart-cut
US7282449B2 (en) 2004-03-05 2007-10-16 S.O.I.Tec Silicon On Insulator Technologies Thermal treatment of a semiconductor layer
FR2867310B1 (fr) 2004-03-05 2006-05-26 Soitec Silicon On Insulator Technique d'amelioration de la qualite d'une couche mince prelevee
US8227319B2 (en) * 2004-03-10 2012-07-24 Agere Systems Inc. Bipolar junction transistor having a high germanium concentration in a silicon-germanium layer and a method for forming the bipolar junction transistor
FR2868202B1 (fr) * 2004-03-25 2006-05-26 Commissariat Energie Atomique Procede de preparation d'une couche de dioxyde de silicium par oxydation a haute temperature sur un substrat presentant au moins en surface du germanium ou un alliage sicicium- germanium.
US7495266B2 (en) 2004-06-16 2009-02-24 Massachusetts Institute Of Technology Strained silicon-on-silicon by wafer bonding and layer transfer
US6893936B1 (en) * 2004-06-29 2005-05-17 International Business Machines Corporation Method of Forming strained SI/SIGE on insulator with silicon germanium buffer
CN100508125C (zh) * 2004-09-24 2009-07-01 信越半导体股份有限公司 半导体晶片的制造方法
JP4617820B2 (ja) * 2004-10-20 2011-01-26 信越半導体株式会社 半導体ウェーハの製造方法
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US7247545B2 (en) * 2004-11-10 2007-07-24 Sharp Laboratories Of America, Inc. Fabrication of a low defect germanium film by direct wafer bonding
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
FR2880988B1 (fr) * 2005-01-19 2007-03-30 Soitec Silicon On Insulator TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE
FR2886053B1 (fr) 2005-05-19 2007-08-10 Soitec Silicon On Insulator Procede de gravure chimique uniforme
FR2886052B1 (fr) 2005-05-19 2007-11-23 Soitec Silicon On Insulator Traitement de surface apres gravure selective
FR2888400B1 (fr) 2005-07-08 2007-10-19 Soitec Silicon On Insulator Procede de prelevement de couche
KR100707654B1 (ko) 2005-07-26 2007-04-13 동부일렉트로닉스 주식회사 반도체 장치의 소자 분리 구조 및 그 형성방법
FR2891281B1 (fr) * 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
FR2892733B1 (fr) * 2005-10-28 2008-02-01 Soitec Silicon On Insulator Relaxation de couches
CN101326646B (zh) 2005-11-01 2011-03-16 麻省理工学院 单片集成的半导体材料和器件
US8063397B2 (en) 2006-06-28 2011-11-22 Massachusetts Institute Of Technology Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission
FR2910179B1 (fr) * 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
FR2912550A1 (fr) * 2007-02-14 2008-08-15 Soitec Silicon On Insulator Procede de fabrication d'une structure ssoi.
JP5256519B2 (ja) 2007-05-03 2013-08-07 ソイテック 洗浄された歪みシリコン表面を作製するための改良されたプロセス
FR2922359B1 (fr) * 2007-10-12 2009-12-18 Commissariat Energie Atomique Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire
FR2947098A1 (fr) * 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
US8492234B2 (en) 2010-06-29 2013-07-23 International Business Machines Corporation Field effect transistor device
US8415253B2 (en) * 2011-03-30 2013-04-09 International Business Machinees Corporation Low-temperature in-situ removal of oxide from a silicon surface during CMOS epitaxial processing
FR2978605B1 (fr) 2011-07-28 2015-10-16 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice comprenant une couche fonctionnalisee sur un substrat support
CN104517883B (zh) * 2013-09-26 2017-08-15 中国科学院上海微系统与信息技术研究所 一种利用离子注入技术制备绝缘体上半导体材料的方法
FR3064398B1 (fr) * 2017-03-21 2019-06-07 Soitec Structure de type semi-conducteur sur isolant, notamment pour un capteur d'image de type face avant, et procede de fabrication d'une telle structure
US20190181218A1 (en) * 2017-12-08 2019-06-13 Qualcomm Incorporated Semiconductor device with high charge carrier mobility materials on porous silicon
GB201916515D0 (en) 2019-11-13 2019-12-25 Pilkington Group Ltd Coated glass substrate

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Also Published As

Publication number Publication date
WO2004006311A3 (en) 2004-03-04
KR20050018984A (ko) 2005-02-28
CN1666330A (zh) 2005-09-07
ATE443344T1 (de) 2009-10-15
JP2005532687A (ja) 2005-10-27
JP4904478B2 (ja) 2012-03-28
US20050191825A1 (en) 2005-09-01
EP1535326A2 (de) 2005-06-01
EP1522097B1 (de) 2009-09-16
FR2842349A1 (fr) 2004-01-16
EP1522097A2 (de) 2005-04-13
WO2004006327A2 (en) 2004-01-15
JP2005532688A (ja) 2005-10-27
CN100477150C (zh) 2009-04-08
EP1522097B9 (de) 2010-03-03
DE60329192D1 (de) 2009-10-22
TWI289900B (en) 2007-11-11
AU2003250462A1 (en) 2004-01-23
WO2004006327A3 (en) 2004-03-04
EP1535326B1 (de) 2009-09-09
TW200411820A (en) 2004-07-01
DE60329293D1 (de) 2009-10-29
AU2003249475A1 (en) 2004-01-23
AU2003250462A8 (en) 2004-01-23
FR2842349B1 (fr) 2005-02-18
KR100796832B1 (ko) 2008-01-22
US6991956B2 (en) 2006-01-31
WO2004006311A2 (en) 2004-01-15

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