ATE524827T1 - Verfahren zum transfer einer schicht gespannten halbleitermaterials - Google Patents

Verfahren zum transfer einer schicht gespannten halbleitermaterials

Info

Publication number
ATE524827T1
ATE524827T1 AT03762846T AT03762846T ATE524827T1 AT E524827 T1 ATE524827 T1 AT E524827T1 AT 03762846 T AT03762846 T AT 03762846T AT 03762846 T AT03762846 T AT 03762846T AT E524827 T1 ATE524827 T1 AT E524827T1
Authority
AT
Austria
Prior art keywords
semiconductor material
layer
lattice parameter
transferring
strained semiconductor
Prior art date
Application number
AT03762846T
Other languages
English (en)
Inventor
Bruno Ghyselen
Daniel Bensahel
Benedicte Osternaud
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE524827T1 publication Critical patent/ATE524827T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1924—Preparing SOI wafers with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Recrystallisation Techniques (AREA)
  • Drying Of Semiconductors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Led Devices (AREA)
AT03762846T 2002-07-09 2003-07-09 Verfahren zum transfer einer schicht gespannten halbleitermaterials ATE524827T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0208602A FR2842350B1 (fr) 2002-07-09 2002-07-09 Procede de transfert d'une couche de materiau semiconducteur contraint
PCT/IB2003/003341 WO2004006326A1 (en) 2002-07-09 2003-07-09 Method of transferring of a layer of strained semiconductor material

Publications (1)

Publication Number Publication Date
ATE524827T1 true ATE524827T1 (de) 2011-09-15

Family

ID=29763665

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03762846T ATE524827T1 (de) 2002-07-09 2003-07-09 Verfahren zum transfer einer schicht gespannten halbleitermaterials

Country Status (9)

Country Link
EP (1) EP1547146B1 (de)
JP (3) JP4545586B2 (de)
KR (1) KR100829644B1 (de)
CN (1) CN100511636C (de)
AT (1) ATE524827T1 (de)
AU (1) AU2003247130A1 (de)
FR (1) FR2842350B1 (de)
TW (1) TWI296836B (de)
WO (1) WO2004006326A1 (de)

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Publication number Priority date Publication date Assignee Title
US7227176B2 (en) 1998-04-10 2007-06-05 Massachusetts Institute Of Technology Etch stop layer system
EP1309989B1 (de) 2000-08-16 2007-01-10 Massachusetts Institute Of Technology Verfahren für die herstellung eines halbleiterartikels mittels graduellem epitaktischen wachsen
US6940089B2 (en) 2001-04-04 2005-09-06 Massachusetts Institute Of Technology Semiconductor device structure
US7074623B2 (en) 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US7307273B2 (en) 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US7335545B2 (en) 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
FR2867310B1 (fr) 2004-03-05 2006-05-26 Soitec Silicon On Insulator Technique d'amelioration de la qualite d'une couche mince prelevee
US7282449B2 (en) 2004-03-05 2007-10-16 S.O.I.Tec Silicon On Insulator Technologies Thermal treatment of a semiconductor layer
FR2867307B1 (fr) 2004-03-05 2006-05-26 Soitec Silicon On Insulator Traitement thermique apres detachement smart-cut
US7217949B2 (en) * 2004-07-01 2007-05-15 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
FR2881877B1 (fr) * 2005-02-04 2007-08-31 Soitec Silicon On Insulator Transistor a effet de champ multi-grille a canal multi-couche
JP4654710B2 (ja) * 2005-02-24 2011-03-23 信越半導体株式会社 半導体ウェーハの製造方法
KR100714822B1 (ko) * 2005-07-29 2007-05-04 한양대학교 산학협력단 에스오아이 웨이퍼의 제조 방법
FR2892733B1 (fr) 2005-10-28 2008-02-01 Soitec Silicon On Insulator Relaxation de couches
FR2883661B1 (fr) * 2006-05-04 2008-04-25 Soitec Silicon On Insulator Transistor a effet de champ multi-grille a canal multi-couche
WO2008149699A1 (en) * 2007-06-01 2008-12-11 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor substrate and semiconductor device
US8178419B2 (en) 2008-02-05 2012-05-15 Twin Creeks Technologies, Inc. Method to texture a lamina surface within a photovoltaic cell
CN103165512A (zh) * 2011-12-14 2013-06-19 中国科学院上海微系统与信息技术研究所 一种超薄绝缘体上半导体材料及其制备方法
US8916954B2 (en) 2012-02-05 2014-12-23 Gtat Corporation Multi-layer metal support
US8841161B2 (en) 2012-02-05 2014-09-23 GTAT.Corporation Method for forming flexible solar cells
US8785294B2 (en) 2012-07-26 2014-07-22 Gtat Corporation Silicon carbide lamina
US20140038329A1 (en) * 2012-08-02 2014-02-06 Gtat Corporation Epitaxial growth on thin lamina
US8946054B2 (en) 2013-04-19 2015-02-03 International Business Machines Corporation Crack control for substrate separation
KR20250069970A (ko) * 2016-01-20 2025-05-20 메사추세츠 인스티튜트 오브 테크놀로지 캐리어 기판 상의 장치의 제조
FR3051595B1 (fr) * 2016-05-17 2022-11-18 Soitec Silicon On Insulator Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant
FR3051596B1 (fr) * 2016-05-17 2022-11-18 Soitec Silicon On Insulator Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant
EP3709943B1 (de) * 2017-11-15 2024-07-24 Smith & Nephew PLC Integrierte sensorgestützte wundüberwachungs- und/oder therapieverbände und -systeme

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3942672B2 (ja) * 1996-04-12 2007-07-11 キヤノンアネルバ株式会社 基板処理方法および基板処理装置
CA2233115C (en) * 1997-03-27 2002-03-12 Canon Kabushiki Kaisha Semiconductor substrate and method of manufacturing the same
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
JP4476390B2 (ja) * 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6323108B1 (en) * 1999-07-27 2001-11-27 The United States Of America As Represented By The Secretary Of The Navy Fabrication ultra-thin bonded semiconductor layers
JP4226175B2 (ja) * 1999-12-10 2009-02-18 富士通株式会社 半導体装置およびその製造方法
KR100429869B1 (ko) * 2000-01-07 2004-05-03 삼성전자주식회사 매몰 실리콘 저머늄층을 갖는 ｃｍｏｓ 집적회로 소자 및기판과 그의 제조방법
JP2003520452A (ja) * 2000-01-20 2003-07-02 アンバーウェーブ システムズ コーポレイション ひずみシリコン酸化金属半導体電界効果トランジスタ
AU2001268577A1 (en) * 2000-06-22 2002-01-02 Massachusetts Institute Of Technology Etch stop layer system
EP1309989B1 (de) * 2000-08-16 2007-01-10 Massachusetts Institute Of Technology Verfahren für die herstellung eines halbleiterartikels mittels graduellem epitaktischen wachsen
US6524935B1 (en) * 2000-09-29 2003-02-25 International Business Machines Corporation Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique
WO2002071493A2 (en) * 2001-03-02 2002-09-12 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed cmos electronics and high speed analog
US6603156B2 (en) * 2001-03-31 2003-08-05 International Business Machines Corporation Strained silicon on insulator structures

Also Published As

Publication number Publication date
CN1666331A (zh) 2005-09-07
AU2003247130A1 (en) 2004-01-23
JP2010199617A (ja) 2010-09-09
CN100511636C (zh) 2009-07-08
FR2842350A1 (fr) 2004-01-16
TW200409281A (en) 2004-06-01
FR2842350B1 (fr) 2005-05-13
TWI296836B (en) 2008-05-11
JP4602475B2 (ja) 2010-12-22
KR20050018979A (ko) 2005-02-28
JP4602474B2 (ja) 2010-12-22
KR100829644B1 (ko) 2008-05-16
WO2004006326A1 (en) 2004-01-15
EP1547146A1 (de) 2005-06-29
JP2010219546A (ja) 2010-09-30
JP4545586B2 (ja) 2010-09-15
EP1547146B1 (de) 2011-09-14
JP2005532686A (ja) 2005-10-27

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