ATE465511T1 - Verfahren zur bildung eines transistors mit einer integrierten metallsilizid-gate-elektrode - Google Patents

Verfahren zur bildung eines transistors mit einer integrierten metallsilizid-gate-elektrode

Info

Publication number
ATE465511T1
ATE465511T1 AT04786450T AT04786450T ATE465511T1 AT E465511 T1 ATE465511 T1 AT E465511T1 AT 04786450 T AT04786450 T AT 04786450T AT 04786450 T AT04786450 T AT 04786450T AT E465511 T1 ATE465511 T1 AT E465511T1
Authority
AT
Austria
Prior art keywords
transistor
metal silicide
forming
gate electrode
trench
Prior art date
Application number
AT04786450T
Other languages
English (en)
Inventor
Todd Abbot
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE465511T1 publication Critical patent/ATE465511T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/0131—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0225—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
AT04786450T 2003-08-15 2004-08-04 Verfahren zur bildung eines transistors mit einer integrierten metallsilizid-gate-elektrode ATE465511T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/641,851 US7012024B2 (en) 2003-08-15 2003-08-15 Methods of forming a transistor with an integrated metal silicide gate electrode
PCT/US2004/025085 WO2005020282A2 (en) 2003-08-15 2004-08-04 Methods of forming a transistor with an integrated metal silicide gate electrode

Publications (1)

Publication Number Publication Date
ATE465511T1 true ATE465511T1 (de) 2010-05-15

Family

ID=34136456

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04786450T ATE465511T1 (de) 2003-08-15 2004-08-04 Verfahren zur bildung eines transistors mit einer integrierten metallsilizid-gate-elektrode

Country Status (9)

Country Link
US (2) US7012024B2 (de)
EP (1) EP1656696B1 (de)
JP (1) JP4826914B2 (de)
KR (1) KR100669627B1 (de)
CN (1) CN100421226C (de)
AT (1) ATE465511T1 (de)
DE (1) DE602004026737D1 (de)
TW (1) TWI245418B (de)
WO (1) WO2005020282A2 (de)

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US7012024B2 (en) 2003-08-15 2006-03-14 Micron Technology, Inc. Methods of forming a transistor with an integrated metal silicide gate electrode
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US7120046B1 (en) 2005-05-13 2006-10-10 Micron Technology, Inc. Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
US7371627B1 (en) * 2005-05-13 2008-05-13 Micron Technology, Inc. Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
US7888721B2 (en) * 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7768051B2 (en) * 2005-07-25 2010-08-03 Micron Technology, Inc. DRAM including a vertical surround gate transistor
US7696567B2 (en) * 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
US7875959B2 (en) * 2005-08-31 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having selective silicide-induced stress and a method of producing same
US7867845B2 (en) * 2005-09-01 2011-01-11 Micron Technology, Inc. Transistor gate forming methods and transistor structures
US7678607B2 (en) 2007-02-05 2010-03-16 Intermolecular, Inc. Methods for forming resistive switching memory elements
US7972897B2 (en) 2007-02-05 2011-07-05 Intermolecular, Inc. Methods for forming resistive switching memory elements
US7704789B2 (en) 2007-02-05 2010-04-27 Intermolecular, Inc. Methods for forming resistive switching memory elements
WO2008109199A1 (en) * 2007-03-05 2008-09-12 Intermolecular, Inc. Methods for forming nonvolatile memory elements with resistive-switching metal oxides
US7629198B2 (en) 2007-03-05 2009-12-08 Intermolecular, Inc. Methods for forming nonvolatile memory elements with resistive-switching metal oxides
US8097878B2 (en) 2007-03-05 2012-01-17 Intermolecular, Inc. Nonvolatile memory elements with metal-deficient resistive-switching metal oxides
US8144498B2 (en) 2007-05-09 2012-03-27 Intermolecular, Inc. Resistive-switching nonvolatile memory elements
WO2009015298A2 (en) 2007-07-25 2009-01-29 Intermolecular, Inc. Nonvolatile memory elements
WO2009015297A1 (en) 2007-07-25 2009-01-29 Intermolecular, Inc. Multistate nonvolatile memory elements
US20090236675A1 (en) * 2008-03-21 2009-09-24 National Tsing Hua University Self-aligned field-effect transistor structure and manufacturing method thereof
KR101604054B1 (ko) * 2009-09-03 2016-03-16 삼성전자주식회사 반도체 소자 및 그 형성방법
US8030196B2 (en) * 2010-01-12 2011-10-04 Samsung Electronics Co., Ltd. Transistor formation using capping layer
CN113594237B (zh) * 2020-04-30 2023-09-26 长鑫存储技术有限公司 埋入式栅极制备方法和半导体器件制备方法
CN111739839B (zh) * 2020-06-23 2021-07-02 武汉新芯集成电路制造有限公司 自对准接触孔的制造方法、半导体器件的制造方法

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Also Published As

Publication number Publication date
EP1656696A2 (de) 2006-05-17
CN1868047A (zh) 2006-11-22
WO2005020282A3 (en) 2006-02-09
TW200511572A (en) 2005-03-16
KR100669627B1 (ko) 2007-01-16
EP1656696B1 (de) 2010-04-21
KR20060032662A (ko) 2006-04-17
US7351659B2 (en) 2008-04-01
CN100421226C (zh) 2008-09-24
US7012024B2 (en) 2006-03-14
JP4826914B2 (ja) 2011-11-30
US20050037584A1 (en) 2005-02-17
WO2005020282A2 (en) 2005-03-03
US20060019457A1 (en) 2006-01-26
EP1656696A4 (de) 2008-07-23
TWI245418B (en) 2005-12-11
DE602004026737D1 (de) 2010-06-02
JP2007503116A (ja) 2007-02-15

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