ATE467905T1 - Integrierte anitfuse-struktur für finfet- und cmos-vorrichtungen - Google Patents

Integrierte anitfuse-struktur für finfet- und cmos-vorrichtungen

Info

Publication number
ATE467905T1
ATE467905T1 AT02808339T AT02808339T ATE467905T1 AT E467905 T1 ATE467905 T1 AT E467905T1 AT 02808339 T AT02808339 T AT 02808339T AT 02808339 T AT02808339 T AT 02808339T AT E467905 T1 ATE467905 T1 AT E467905T1
Authority
AT
Austria
Prior art keywords
corners
layer
finfet
semiconducting material
integrated
Prior art date
Application number
AT02808339T
Other languages
English (en)
Inventor
Jed Rankin
Wagdi Abadeer
Jeffrey Brown
Kiran Chatty
William Tonti
Robert Gauthier
David Fried
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE467905T1 publication Critical patent/ATE467905T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H10W20/491—Antifuses, i.e. interconnections changeable from non-conductive to conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6212—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies having non-rectangular cross-sections
    • H10D30/6213—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies having non-rectangular cross-sections having rounded corners

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Formation Of Insulating Films (AREA)
AT02808339T 2002-12-20 2002-12-20 Integrierte anitfuse-struktur für finfet- und cmos-vorrichtungen ATE467905T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2002/041182 WO2004059726A1 (en) 2002-12-20 2002-12-20 Integrated antifuse structure for finfet and cmos devices

Publications (1)

Publication Number Publication Date
ATE467905T1 true ATE467905T1 (de) 2010-05-15

Family

ID=32679942

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02808339T ATE467905T1 (de) 2002-12-20 2002-12-20 Integrierte anitfuse-struktur für finfet- und cmos-vorrichtungen

Country Status (7)

Country Link
EP (1) EP1581968B1 (de)
JP (1) JP4418760B2 (de)
CN (1) CN1314124C (de)
AT (1) ATE467905T1 (de)
AU (1) AU2002368525A1 (de)
DE (1) DE60236375D1 (de)
WO (1) WO2004059726A1 (de)

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US7358121B2 (en) 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7105390B2 (en) 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US7624192B2 (en) 2003-12-30 2009-11-24 Microsoft Corporation Framework for user interaction with multiple network devices
US7268058B2 (en) 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7579280B2 (en) 2004-06-01 2009-08-25 Intel Corporation Method of patterning a film
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7332439B2 (en) 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7361958B2 (en) 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7193279B2 (en) 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060202266A1 (en) 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7402875B2 (en) 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US8030736B2 (en) * 2009-08-10 2011-10-04 International Business Machines Corporation Fin anti-fuse with reduced programming voltage
US9159734B2 (en) 2011-10-18 2015-10-13 Intel Corporation Antifuse element utilizing non-planar topology
US9536883B2 (en) * 2012-07-12 2017-01-03 Broadcom Corporation Dual anti-fuse
CN103730367B (zh) * 2012-10-16 2017-05-03 中国科学院微电子研究所 半导体器件制造方法
US11515251B2 (en) * 2018-04-02 2022-11-29 Intel Corporation FinFET transistors as antifuse elements

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US5322812A (en) 1991-03-20 1994-06-21 Crosspoint Solutions, Inc. Improved method of fabricating antifuses in an integrated circuit device and resulting structure
US5557136A (en) * 1991-04-26 1996-09-17 Quicklogic Corporation Programmable interconnect structures and programmable integrated circuits
US5475253A (en) 1992-08-21 1995-12-12 Xilinx, Inc. Antifuse structure with increased breakdown at edges
US5572062A (en) * 1994-03-31 1996-11-05 Crosspoint Solutions, Inc. Antifuse with silicon spacers
TW347587B (en) * 1997-10-20 1998-12-11 United Semiconductor Corp Antifuse structure and process for producing the same
US6130469A (en) * 1998-04-24 2000-10-10 International Business Machines Corporation Electrically alterable antifuse using FET
US6096580A (en) 1999-09-24 2000-08-01 International Business Machines Corporation Low programming voltage anti-fuse
US6150234A (en) 1999-12-16 2000-11-21 Vlsi Technology, Inc. Trench-diffusion corner rounding in a shallow-trench (STI) process
US6774439B2 (en) * 2000-02-17 2004-08-10 Kabushiki Kaisha Toshiba Semiconductor device using fuse/anti-fuse system
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture

Also Published As

Publication number Publication date
CN1714439A (zh) 2005-12-28
EP1581968B1 (de) 2010-05-12
EP1581968A1 (de) 2005-10-05
EP1581968A4 (de) 2007-04-18
DE60236375D1 (de) 2010-06-24
JP4418760B2 (ja) 2010-02-24
CN1314124C (zh) 2007-05-02
AU2002368525A1 (en) 2004-07-22
JP2006511093A (ja) 2006-03-30
WO2004059726A1 (en) 2004-07-15

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