ATE478376T1 - Arithmetische logik und schaltvorrichtung zur verwendung in einem prozessor - Google Patents

Arithmetische logik und schaltvorrichtung zur verwendung in einem prozessor

Info

Publication number
ATE478376T1
ATE478376T1 AT06846216T AT06846216T ATE478376T1 AT E478376 T1 ATE478376 T1 AT E478376T1 AT 06846216 T AT06846216 T AT 06846216T AT 06846216 T AT06846216 T AT 06846216T AT E478376 T1 ATE478376 T1 AT E478376T1
Authority
AT
Austria
Prior art keywords
input
receive
arithmetic logic
output
arithmetic
Prior art date
Application number
AT06846216T
Other languages
English (en)
Inventor
Muhammad Ahmed
Ajay Anant Ingle
Sujat Jamil
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Application granted granted Critical
Publication of ATE478376T1 publication Critical patent/ATE478376T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181Instruction operation extension or modification
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/3012Organisation of register space, e.g. banked or distributed register file
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181Instruction operation extension or modification
    • G06F9/30189Instruction operation extension or modification according to execution mode, e.g. mode flag
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802Instruction prefetching
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Hardware Redundancy (AREA)
AT06846216T 2005-11-02 2006-11-02 Arithmetische logik und schaltvorrichtung zur verwendung in einem prozessor ATE478376T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/266,076 US8099448B2 (en) 2005-11-02 2005-11-02 Arithmetic logic and shifting device for use in a processor
PCT/US2006/060500 WO2007056675A2 (en) 2005-11-02 2006-11-02 Arithmethic logic and shifting device for use in a processor

Publications (1)

Publication Number Publication Date
ATE478376T1 true ATE478376T1 (de) 2010-09-15

Family

ID=37983462

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06846216T ATE478376T1 (de) 2005-11-02 2006-11-02 Arithmetische logik und schaltvorrichtung zur verwendung in einem prozessor

Country Status (7)

Country Link
US (2) US8099448B2 (de)
EP (2) EP2256948B1 (de)
CN (2) CN102591619B (de)
AT (1) ATE478376T1 (de)
DE (1) DE602006016315D1 (de)
TW (1) TW200746657A (de)
WO (1) WO2007056675A2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8099448B2 (en) 2005-11-02 2012-01-17 Qualcomm Incorporated Arithmetic logic and shifting device for use in a processor
US20130019053A1 (en) * 2011-07-14 2013-01-17 Vinay Ashok Somanache Flash controller hardware architecture for flash devices
CN103389903A (zh) * 2012-05-07 2013-11-13 北京大学深圳研究生院 一种功能可配置的数字信号处理单元
US10311085B2 (en) 2012-08-31 2019-06-04 Netseer, Inc. Concept-level user intent profile extraction and applications
US20150178078A1 (en) * 2013-12-21 2015-06-25 H. Peter Anvin Instructions and logic to provide base register swap status verification functionality
US10223002B2 (en) * 2017-02-08 2019-03-05 Arm Limited Compare-and-swap transaction
US10963265B2 (en) * 2017-04-21 2021-03-30 Micron Technology, Inc. Apparatus and method to switch configurable logic units
CN109614145B (zh) * 2018-10-18 2021-03-09 中国科学院计算技术研究所 一种处理器核心结构及数据访存方法
TWI786543B (zh) * 2021-02-17 2022-12-11 韋僑科技股份有限公司 無線通訊模組及其應用裝置控制系統與應用裝置控制方法

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US3916388A (en) * 1974-05-30 1975-10-28 Ibm Shifting apparatus for automatic data alignment
US4654781A (en) * 1981-10-02 1987-03-31 Raytheon Company Byte addressable memory for variable length instructions and data
ATE82412T1 (de) * 1986-02-06 1992-11-15 Mips Computer Systems Inc Funktionseinheit fuer rechner.
EP0601715A1 (de) * 1992-12-11 1994-06-15 National Semiconductor Corporation Für den On-Chip-Speicherzugriff optimierter CPV-Kernbus
US5450607A (en) * 1993-05-17 1995-09-12 Mips Technologies Inc. Unified floating point and integer datapath for a RISC processor
JPH06332792A (ja) * 1993-05-21 1994-12-02 Mitsubishi Electric Corp データ処理装置及びそのデータ読み出し制御回路,データ書き込み制御回路
US5933651A (en) * 1995-09-29 1999-08-03 Matsushita Electric Works, Ltd. Programmable controller
JP3546980B2 (ja) * 1996-03-29 2004-07-28 松下電器産業株式会社 データ処理装置
US5922066A (en) * 1997-02-24 1999-07-13 Samsung Electronics Co., Ltd. Multifunction data aligner in wide data width processor
US6061779A (en) * 1998-01-16 2000-05-09 Analog Devices, Inc. Digital signal processor having data alignment buffer for performing unaligned data accesses
US6574724B1 (en) * 2000-02-18 2003-06-03 Texas Instruments Incorporated Microprocessor with non-aligned scaled and unscaled addressing
US6714233B2 (en) 2000-06-21 2004-03-30 Seiko Epson Corporation Mobile video telephone system
US6785887B2 (en) 2000-12-27 2004-08-31 International Business Machines Corporation Technique for using shared resources on a multi-threaded processor
JP3776732B2 (ja) * 2001-02-02 2006-05-17 株式会社東芝 プロセッサ装置
US6721866B2 (en) * 2001-12-21 2004-04-13 Intel Corporation Unaligned memory operands
EP1326228B1 (de) * 2002-01-04 2016-03-23 MediaLab Solutions LLC Verfahren und Vorrichtung zur Erzeugung, zur Veränderung, zur Wechselwirkung und zum Spielen von Musikstücken
US6476634B1 (en) 2002-02-01 2002-11-05 Xilinx, Inc. ALU implementation in single PLD logic cell
US8074051B2 (en) 2004-04-07 2011-12-06 Aspen Acquisition Corporation Multithreaded processor with multiple concurrent pipelines per thread
US7328332B2 (en) * 2004-08-30 2008-02-05 Texas Instruments Incorporated Branch prediction and other processor improvements using FIFO for bypassing certain processor pipeline stages
US7676646B2 (en) * 2005-03-02 2010-03-09 Cisco Technology, Inc. Packet processor with wide register set architecture
US8099448B2 (en) 2005-11-02 2012-01-17 Qualcomm Incorporated Arithmetic logic and shifting device for use in a processor

Also Published As

Publication number Publication date
WO2007056675A3 (en) 2007-09-13
DE602006016315D1 (de) 2010-09-30
WO2007056675A2 (en) 2007-05-18
EP1943588B1 (de) 2010-08-18
US20070100923A1 (en) 2007-05-03
US8688761B2 (en) 2014-04-01
EP2256948A2 (de) 2010-12-01
CN102591619A (zh) 2012-07-18
EP2256948A3 (de) 2014-03-19
EP1943588A2 (de) 2008-07-16
CN101346694A (zh) 2009-01-14
US20120083912A1 (en) 2012-04-05
US8099448B2 (en) 2012-01-17
CN101346694B (zh) 2011-12-14
CN102591619B (zh) 2016-04-06
TW200746657A (en) 2007-12-16
EP2256948B1 (de) 2015-04-22

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