ATE484027T1 - Dynamische cache-speicherung von engine- anweisungen für die auf-bedarf-programmausführung - Google Patents

Dynamische cache-speicherung von engine- anweisungen für die auf-bedarf-programmausführung

Info

Publication number
ATE484027T1
ATE484027T1 AT04796714T AT04796714T ATE484027T1 AT E484027 T1 ATE484027 T1 AT E484027T1 AT 04796714 T AT04796714 T AT 04796714T AT 04796714 T AT04796714 T AT 04796714T AT E484027 T1 ATE484027 T1 AT E484027T1
Authority
AT
Austria
Prior art keywords
program execution
cache storage
demand program
dynamic cache
engine instructions
Prior art date
Application number
AT04796714T
Other languages
English (en)
Inventor
Sridhar Lakshmanamurthy
Wilson Liao
Prashant Chandra
Jeen-Yuan Min
Yim Pun
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE484027T1 publication Critical patent/ATE484027T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30047—Prefetch instructions; cache control instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3063—Pipelined operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Small-Scale Networks (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)
AT04796714T 2003-11-06 2004-10-29 Dynamische cache-speicherung von engine- anweisungen für die auf-bedarf-programmausführung ATE484027T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/704,432 US20050102474A1 (en) 2003-11-06 2003-11-06 Dynamically caching engine instructions
PCT/US2004/035923 WO2005048113A2 (en) 2003-11-06 2004-10-29 Dynamically caching engine instructions for on demand program execution

Publications (1)

Publication Number Publication Date
ATE484027T1 true ATE484027T1 (de) 2010-10-15

Family

ID=34552126

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04796714T ATE484027T1 (de) 2003-11-06 2004-10-29 Dynamische cache-speicherung von engine- anweisungen für die auf-bedarf-programmausführung

Country Status (7)

Country Link
US (1) US20050102474A1 (de)
EP (1) EP1680743B1 (de)
JP (1) JP2007510989A (de)
CN (1) CN1997973B (de)
AT (1) ATE484027T1 (de)
DE (1) DE602004029485D1 (de)
WO (1) WO2005048113A2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7376789B2 (en) * 2005-06-29 2008-05-20 Intel Corporation Wide-port context cache apparatus, systems, and methods
US20070005898A1 (en) * 2005-06-30 2007-01-04 William Halleck Method, apparatus and system for task context cache replacement
US7676604B2 (en) * 2005-11-22 2010-03-09 Intel Corporation Task context direct indexing in a protocol engine
US8166277B2 (en) * 2008-02-01 2012-04-24 International Business Machines Corporation Data prefetching using indirect addressing
US8209488B2 (en) * 2008-02-01 2012-06-26 International Business Machines Corporation Techniques for prediction-based indirect data prefetching
CN102571761B (zh) * 2011-12-21 2014-08-20 四川长虹电器股份有限公司 网络接口的信息传输方法
US10095847B2 (en) * 2012-05-25 2018-10-09 Koninklijke Philips N.V. Method, system and device for protection against reverse engineering and/or tampering with programs
CN102855213B (zh) * 2012-07-06 2017-10-27 中兴通讯股份有限公司 一种网络处理器指令存储装置及该装置的指令存储方法
US9223705B2 (en) * 2013-04-01 2015-12-29 Advanced Micro Devices, Inc. Cache access arbitration for prefetch requests
US9286258B2 (en) 2013-06-14 2016-03-15 National Instruments Corporation Opaque bridge for peripheral component interconnect express bus systems
US11397520B2 (en) 2013-08-01 2022-07-26 Yogesh Chunilal Rathod Application program interface or page processing method and device
WO2015015251A1 (en) * 2013-08-01 2015-02-05 Yogesh Chunilal Rathod Presenting plurality types of interfaces and functions for conducting various activities
CN113326020B (zh) 2020-02-28 2025-04-25 昆仑芯(北京)科技有限公司 缓存器件、缓存器、系统、数据处理方法、装置及介质
WO2022088074A1 (zh) * 2020-10-30 2022-05-05 华为技术有限公司 基于多指令引擎的指令处理方法及处理器
CN116151338A (zh) * 2021-11-19 2023-05-23 平头哥(上海)半导体技术有限公司 高速缓存的访问方法以及相关图神经网络系统

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60263238A (ja) * 1984-06-11 1985-12-26 Nippon Telegr & Teleph Corp <Ntt> 情報処理装置
JPH03268041A (ja) * 1990-03-17 1991-11-28 Res Dev Corp Of Japan キャッシュ操作明示化コンピュータ
US6021471A (en) * 1994-11-15 2000-02-01 Advanced Micro Devices, Inc. Multiple level cache control system with address and data pipelines
JPH096633A (ja) * 1995-06-07 1997-01-10 Internatl Business Mach Corp <Ibm> データ処理システムに於ける高性能多重論理経路の動作用の方法とシステム
JPH09282223A (ja) * 1996-04-12 1997-10-31 Ricoh Co Ltd メモリ制御装置
US6446143B1 (en) * 1998-11-25 2002-09-03 Compaq Information Technologies Group, L.P. Methods and apparatus for minimizing the impact of excessive instruction retrieval
JP3420091B2 (ja) * 1998-11-30 2003-06-23 Ｎｅｃエレクトロニクス株式会社 マイクロプロセッサ
US6393551B1 (en) * 1999-05-26 2002-05-21 Infineon Technologies North America Corp. Reducing instruction transactions in a microprocessor
US6985431B1 (en) * 1999-08-27 2006-01-10 International Business Machines Corporation Network switch and components and method of operation
US6668317B1 (en) * 1999-08-31 2003-12-23 Intel Corporation Microengine for parallel processor architecture
US6606704B1 (en) * 1999-08-31 2003-08-12 Intel Corporation Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode
JP3741945B2 (ja) * 1999-09-30 2006-02-01 富士通株式会社 命令フェッチ制御装置
US6574712B1 (en) * 1999-11-08 2003-06-03 International Business Machines Corporation Software prefetch system and method for predetermining amount of streamed data
US6470427B1 (en) * 1999-11-09 2002-10-22 International Business Machines Corporation Programmable agent and method for managing prefetch queues
JP2001236221A (ja) * 2000-02-21 2001-08-31 Keisuke Shindo マルチスレッドを利用するパイプライン並列プロセッサ
JP2001344153A (ja) * 2000-05-30 2001-12-14 Nec Corp マルチプロセッサシステムのキャッシュメモリ制御装置
JP2002132702A (ja) * 2000-10-30 2002-05-10 Nec Eng Ltd メモリ制御方式
US20020181476A1 (en) * 2001-03-17 2002-12-05 Badamo Michael J. Network infrastructure device for data traffic to and from mobile units
US7487505B2 (en) * 2001-08-27 2009-02-03 Intel Corporation Multithreaded microprocessor with register allocation based on number of active threads
US7120755B2 (en) * 2002-01-02 2006-10-10 Intel Corporation Transfer of cache lines on-chip between processing cores in a multi-core system
US6915415B2 (en) * 2002-01-07 2005-07-05 International Business Machines Corporation Method and apparatus for mapping software prefetch instructions to hardware prefetch logic
US20050050306A1 (en) * 2003-08-26 2005-03-03 Sridhar Lakshmanamurthy Executing instructions on a processor

Also Published As

Publication number Publication date
EP1680743A2 (de) 2006-07-19
US20050102474A1 (en) 2005-05-12
JP2007510989A (ja) 2007-04-26
WO2005048113A2 (en) 2005-05-26
WO2005048113A3 (en) 2006-11-23
DE602004029485D1 (de) 2010-11-18
EP1680743B1 (de) 2010-10-06
CN1997973A (zh) 2007-07-11
CN1997973B (zh) 2010-06-09

Similar Documents

Publication Publication Date Title
DE602004029485D1 (de) Dynamische cache-speicherung von engine-anweisungen für die auf-bedarf-programmausführung
WO2004068339A3 (en) Multithreaded processor with recoupled data and instruction prefetch
TW200517955A (en) System and method for handling exceptional instructions in a trace cache based processor
ATE483202T1 (de) Verfahren und vorrichtungen zur bereitstellung eines software-implementierten cache-speichers
TW200518480A (en) Method for firmware variable storage with eager compression, fail-safe extraction and restart time compression scan
GB2463828A (en) Technique for preserving cached information during low power mode
DE602007006276D1 (de) Effiziente speicherhierarchieverwaltung
TW200736908A (en) Memory system and memory management method including the same
WO2006105416A3 (en) System and method to determine a simplified representation of a model
DE502006006470D1 (de) Kolben für eine brennkraftmaschine
EP1349063A3 (de) Programm-Simulation mit Kompilierung während der Laufzeit
ATE437300T1 (de) Verbrennungsmotor
TW200723094A (en) Dynamic branch prediction system and method
EP2527978A3 (de) Verfahren zur Auswahl zwischen einer vorbestimmten Anzahl von Ausführungsmethoden für ein Anwendungsprogramm
ATE521874T1 (de) Informationspunkt
ATE555589T1 (de) Benutzeroberflächen für ein in einem verteilten system angeordnetes dienstobjekt
ATE459917T1 (de) Verringern von mit privaten variablen in parallelen programmen assoziiertem speicherreferenz-overhead
ATE418106T1 (de) Generisches suchverfahren für verschiedenen objekttypen
WO2007032800A3 (en) Hashing assist for network processors
DE602004028540D1 (de) Polymorphismus zur Laufzeit
DE50210759D1 (de) Prozessor mit interner speicherkonfiguration und anordnung mit diesem prozessor
DE602004032572D1 (de) Spezieller cache-speicher
EP1632846A3 (de) System und Verfahren zur Laufzeit-Verfolgung von Werte
TW200615758A (en) K-way direct mapped cache
ATE553291T1 (de) Abschirmteil

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties