ATE495494T1 - Speicherschnittstelle für flüchtige und nichtflüchtige speicherbausteine - Google Patents

Speicherschnittstelle für flüchtige und nichtflüchtige speicherbausteine

Info

Publication number
ATE495494T1
ATE495494T1 AT06711061T AT06711061T ATE495494T1 AT E495494 T1 ATE495494 T1 AT E495494T1 AT 06711061 T AT06711061 T AT 06711061T AT 06711061 T AT06711061 T AT 06711061T AT E495494 T1 ATE495494 T1 AT E495494T1
Authority
AT
Austria
Prior art keywords
volatile
memory
interface
data
memory device
Prior art date
Application number
AT06711061T
Other languages
English (en)
Inventor
Jani Klint
Sakari Sippola
Matti Floman
Jukka-Pekka Vihmalo
Original Assignee
Nokia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Corp filed Critical Nokia Corp
Application granted granted Critical
Publication of ATE495494T1 publication Critical patent/ATE495494T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
AT06711061T 2005-04-12 2006-03-09 Speicherschnittstelle für flüchtige und nichtflüchtige speicherbausteine ATE495494T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/105,324 US7702839B2 (en) 2005-04-12 2005-04-12 Memory interface for volatile and non-volatile memory devices
PCT/IB2006/050738 WO2006109201A2 (en) 2005-04-12 2006-03-09 Memory interface for volatile and non-volatile memory devices

Publications (1)

Publication Number Publication Date
ATE495494T1 true ATE495494T1 (de) 2011-01-15

Family

ID=37084415

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06711061T ATE495494T1 (de) 2005-04-12 2006-03-09 Speicherschnittstelle für flüchtige und nichtflüchtige speicherbausteine

Country Status (10)

Country Link
US (2) US7702839B2 (de)
EP (1) EP1869560B1 (de)
JP (1) JP2008536230A (de)
KR (2) KR101140723B1 (de)
CN (1) CN101180617B (de)
AT (1) ATE495494T1 (de)
DE (1) DE602006019571D1 (de)
MY (1) MY143636A (de)
TW (1) TWI435334B (de)
WO (1) WO2006109201A2 (de)

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Also Published As

Publication number Publication date
KR20090125847A (ko) 2009-12-07
US8635394B2 (en) 2014-01-21
KR100948090B1 (ko) 2010-03-16
KR20070120596A (ko) 2007-12-24
US20060230250A1 (en) 2006-10-12
JP2008536230A (ja) 2008-09-04
TW200643970A (en) 2006-12-16
WO2006109201A3 (en) 2007-02-08
CN101180617B (zh) 2010-05-19
TWI435334B (zh) 2014-04-21
WO2006109201A2 (en) 2006-10-19
DE602006019571D1 (de) 2011-02-24
KR101140723B1 (ko) 2012-05-24
EP1869560B1 (de) 2011-01-12
CN101180617A (zh) 2008-05-14
EP1869560A2 (de) 2007-12-26
US20080162768A1 (en) 2008-07-03
US7702839B2 (en) 2010-04-20
MY143636A (en) 2011-06-15

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