ATE501479T1 - Gerät und verfahren für auswählbare hardware- beschleuniger in einer datengesteuerten architektur - Google Patents

Gerät und verfahren für auswählbare hardware- beschleuniger in einer datengesteuerten architektur

Info

Publication number
ATE501479T1
ATE501479T1 AT04753354T AT04753354T ATE501479T1 AT E501479 T1 ATE501479 T1 AT E501479T1 AT 04753354 T AT04753354 T AT 04753354T AT 04753354 T AT04753354 T AT 04753354T AT E501479 T1 ATE501479 T1 AT E501479T1
Authority
AT
Austria
Prior art keywords
hardware accelerators
data
driven architecture
selection unit
processing elements
Prior art date
Application number
AT04753354T
Other languages
English (en)
Inventor
Louis Lippincott
Patrick Johnson
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE501479T1 publication Critical patent/ATE501479T1/de

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/50—Indexing scheme relating to G06F9/50
    • G06F2209/507—Low-level

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
AT04753354T 2003-06-23 2004-05-26 Gerät und verfahren für auswählbare hardware- beschleuniger in einer datengesteuerten architektur ATE501479T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/601,617 US7714870B2 (en) 2003-06-23 2003-06-23 Apparatus and method for selectable hardware accelerators in a data driven architecture
PCT/US2004/016511 WO2005001685A1 (en) 2003-06-23 2004-05-26 An apparatus and method for selectable hardware accelerators in a data driven architecture

Publications (1)

Publication Number Publication Date
ATE501479T1 true ATE501479T1 (de) 2011-03-15

Family

ID=33517998

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04753354T ATE501479T1 (de) 2003-06-23 2004-05-26 Gerät und verfahren für auswählbare hardware- beschleuniger in einer datengesteuerten architektur

Country Status (9)

Country Link
US (3) US7714870B2 (de)
EP (1) EP1636695B1 (de)
JP (1) JP2007520766A (de)
KR (1) KR100880300B1 (de)
AT (1) ATE501479T1 (de)
DE (1) DE602004031729D1 (de)
MY (1) MY146717A (de)
TW (1) TWI251750B (de)
WO (1) WO2005001685A1 (de)

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Also Published As

Publication number Publication date
TWI251750B (en) 2006-03-21
JP2007520766A (ja) 2007-07-26
US8063907B2 (en) 2011-11-22
US7714870B2 (en) 2010-05-11
US8754893B2 (en) 2014-06-17
EP1636695B1 (de) 2011-03-09
MY146717A (en) 2012-09-14
EP1636695A1 (de) 2006-03-22
WO2005001685A1 (en) 2005-01-06
US20120032964A1 (en) 2012-02-09
DE602004031729D1 (de) 2011-04-21
KR100880300B1 (ko) 2009-01-28
KR20060027808A (ko) 2006-03-28
TW200504526A (en) 2005-02-01
US20090309884A1 (en) 2009-12-17
US20040257370A1 (en) 2004-12-23

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