ATE502337T1 - Multi-bank speicher-untersystem mit anordnung von mehreren speichermodulen - Google Patents

Multi-bank speicher-untersystem mit anordnung von mehreren speichermodulen

Info

Publication number
ATE502337T1
ATE502337T1 AT02719433T AT02719433T ATE502337T1 AT E502337 T1 ATE502337 T1 AT E502337T1 AT 02719433 T AT02719433 T AT 02719433T AT 02719433 T AT02719433 T AT 02719433T AT E502337 T1 ATE502337 T1 AT E502337T1
Authority
AT
Austria
Prior art keywords
memory
bank
coupled
modules
bus
Prior art date
Application number
AT02719433T
Other languages
English (en)
Inventor
Lam Dong
Original Assignee
Oracle America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oracle America Inc filed Critical Oracle America Inc
Application granted granted Critical
Publication of ATE502337T1 publication Critical patent/ATE502337T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/409—Mechanical coupling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Multi Processors (AREA)
AT02719433T 2001-03-30 2002-03-29 Multi-bank speicher-untersystem mit anordnung von mehreren speichermodulen ATE502337T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/823,540 US6725314B1 (en) 2001-03-30 2001-03-30 Multi-bank memory subsystem employing an arrangement of multiple memory modules
PCT/US2002/010563 WO2002080002A2 (en) 2001-03-30 2002-03-29 Multi-bank memory subsystem employing an arrangement of multiple memory modules

Publications (1)

Publication Number Publication Date
ATE502337T1 true ATE502337T1 (de) 2011-04-15

Family

ID=25239051

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02719433T ATE502337T1 (de) 2001-03-30 2002-03-29 Multi-bank speicher-untersystem mit anordnung von mehreren speichermodulen

Country Status (10)

Country Link
US (1) US6725314B1 (de)
EP (1) EP1374073B1 (de)
JP (1) JP3806089B2 (de)
KR (1) KR20030085134A (de)
CN (1) CN1328676C (de)
AT (1) ATE502337T1 (de)
AU (1) AU2002250514A1 (de)
CA (1) CA2437565C (de)
DE (1) DE60239451D1 (de)
WO (1) WO2002080002A2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6996644B2 (en) * 2001-06-06 2006-02-07 Conexant Systems, Inc. Apparatus and methods for initializing integrated circuit addresses
KR100448717B1 (ko) * 2002-08-02 2004-09-13 삼성전자주식회사 메모리 시스템
US6996686B2 (en) * 2002-12-23 2006-02-07 Sun Microsystems, Inc. Memory subsystem including memory modules having multiple banks
US7533218B2 (en) * 2003-11-17 2009-05-12 Sun Microsystems, Inc. Memory system topology
JP2006004079A (ja) * 2004-06-16 2006-01-05 Sony Corp 記憶装置
US7350048B1 (en) 2004-10-28 2008-03-25 Sun Microsystems, Inc. Memory system topology
KR100763352B1 (ko) * 2005-05-10 2007-10-04 삼성전자주식회사 전용 데이터 및 컨트롤 버스들을 사용하는 메모리 시스템, 모듈들, 컨트롤러들 및 방법들
US7577760B2 (en) 2005-05-10 2009-08-18 Samsung Electronics Co., Ltd. Memory systems, modules, controllers and methods using dedicated data and control busses
US7496777B2 (en) * 2005-10-12 2009-02-24 Sun Microsystems, Inc. Power throttling in a memory system
US7533212B1 (en) 2005-10-20 2009-05-12 Sun Microsystems, Inc. System memory board subsystem using DRAM with integrated high speed point to point links
US7523282B1 (en) 2005-10-27 2009-04-21 Sun Microsystems, Inc. Clock enable throttling for power savings in a memory subsystem
US7409491B2 (en) * 2005-12-14 2008-08-05 Sun Microsystems, Inc. System memory board subsystem using DRAM with stacked dedicated high speed point to point links
US8380940B2 (en) * 2010-06-25 2013-02-19 Qualcomm Incorporated Multi-channel multi-port memory
US9432298B1 (en) 2011-12-09 2016-08-30 P4tents1, LLC System, method, and computer program product for improving memory systems
US9285865B2 (en) 2012-06-29 2016-03-15 Oracle International Corporation Dynamic link scaling based on bandwidth utilization
US20150016046A1 (en) * 2013-07-10 2015-01-15 Samsung Electronics Co., Ltd. Ina cabled memory appliance

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4025903A (en) 1973-09-10 1977-05-24 Computer Automation, Inc. Automatic modular memory address allocation system
GB2226665A (en) 1988-12-30 1990-07-04 Copam Electronics Corp Computer memory structure
US5089993B1 (en) 1989-09-29 1998-12-01 Texas Instruments Inc Memory module arranged for data and parity bits
US5226134A (en) * 1990-10-01 1993-07-06 International Business Machines Corp. Data processing system including a memory controller for direct or interleave memory accessing
US5270964A (en) 1992-05-19 1993-12-14 Sun Microsystems, Inc. Single in-line memory module
US5265218A (en) 1992-05-19 1993-11-23 Sun Microsystems, Inc. Bus architecture for integrated data and video memory
US5530623A (en) * 1993-11-19 1996-06-25 Ncr Corporation High speed memory packaging scheme
US5881264A (en) * 1996-01-31 1999-03-09 Kabushiki Kaisha Toshiba Memory controller and memory control system
KR100203145B1 (ko) 1996-06-29 1999-06-15 김영환 반도체 메모리 소자의 뱅크 분산 방법
US6202110B1 (en) 1997-03-31 2001-03-13 International Business Machines Corporation Memory cards with symmetrical pinout for back-to-back mounting in computer system
US5796672A (en) * 1997-04-24 1998-08-18 Texas Instruments Incorporated Method and circuit for routing data to registers in an integrated circuit
US6330627B1 (en) * 1998-01-20 2001-12-11 Kabushiki Kaisha Toshiba System for fast data transfer between memory modules and controller using two clock lines each having a go line portion and a return line portion

Also Published As

Publication number Publication date
WO2002080002A2 (en) 2002-10-10
JP3806089B2 (ja) 2006-08-09
DE60239451D1 (de) 2011-04-28
JP2004524628A (ja) 2004-08-12
US6725314B1 (en) 2004-04-20
KR20030085134A (ko) 2003-11-03
CA2437565C (en) 2005-05-17
CA2437565A1 (en) 2002-10-10
CN1328676C (zh) 2007-07-25
CN1514972A (zh) 2004-07-21
EP1374073B1 (de) 2011-03-16
EP1374073A2 (de) 2004-01-02
AU2002250514A1 (en) 2002-10-15
WO2002080002A3 (en) 2002-11-21

Similar Documents

Publication Publication Date Title
DE60239451D1 (de) Multi-bank speicher-untersystem mit anordnung von mehreren speichermodulen
ATE372551T1 (de) Speichersystem mit speichermodulen und mehrerer speicherbänke
KR960026780A (ko) 단일/이중 인-라인 메모리 모듈에 패키징되는 동기식 메모리 및 제조 방법
DE602005008560D1 (de) Dynamisches befehls- und/oder adressenspiegelungssystem und verfahren für speichermodule
DE602004017029D1 (de) Mehrprozessorsystem und -verfahren mit mehreren speicher-hub-modulen
US7411843B2 (en) Semiconductor memory arrangement with branched control and address bus
JPS62149093A (ja) 連続したアドレススペ−スを与えるメモリシステム
DE60016220D1 (de) Speichererweiterungsmodul mit einer vielzahl von speicherbanken und einer banksteuerungschaltung
US20120250264A1 (en) Memory module having memory chip and register buffer
DE50000882D1 (de) Speicheranordnung mit adressverwürfelung
KR880010421A (ko) 오픈 비트선 구조를 가지는 다이나믹형 랜덤 억세스 메모리
WO2003041119A3 (en) Improved architecture with shared memory
TW200615970A (en) Hierarchical module
KR920010632A (ko) 반도체 메모리 디바이스
ATE387668T1 (de) Befehls- und adressenbustopologie mit aufgeteiltem t-ketten-speicher
TW200701250A (en) Semiconductor memory
WO2012006609A3 (en) Memory devices and methods having multiple address accesses in same cycle
ATE409347T1 (de) Zirkulator-ketten-speicher-befehls- und - adressenbustopologie
KR960009150A (ko) 반도체 메모리소자
US20070194446A1 (en) Memory module comprising an electronic printed circuit board and a plurality of semiconductor components and method
DK1488427T3 (da) Volumetrisk datalagringsapparat omfattende en flerhed af stablede matrixadresserbare hukommelsesindretninger
KR970023398A (ko) 반도체 메모리장치의 데이타라인의 구조 및 그 배치방법
Lefter et al. A shared polyhedral cache for 3d wide-i/o multi-core computing platforms
KR100380023B1 (ko) 단변 방향의 칩 사이즈를 줄일 수 있는 반도체메모리장치
KR960036052A (ko) 로우리던던시기능을 가지는 반도체메모리장치

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties