ATE508412T1 - Kohärenzsteuerungsvorrichtung für eine mehrprozessorvorrichtung, modul und multimodularchitektur-mehrprozessorvorrichtung mit einer derartigen steuervorrichtung - Google Patents

Kohärenzsteuerungsvorrichtung für eine mehrprozessorvorrichtung, modul und multimodularchitektur-mehrprozessorvorrichtung mit einer derartigen steuervorrichtung

Info

Publication number
ATE508412T1
ATE508412T1 AT02290336T AT02290336T ATE508412T1 AT E508412 T1 ATE508412 T1 AT E508412T1 AT 02290336 T AT02290336 T AT 02290336T AT 02290336 T AT02290336 T AT 02290336T AT E508412 T1 ATE508412 T1 AT E508412T1
Authority
AT
Austria
Prior art keywords
module
coherence
control device
cache
modules
Prior art date
Application number
AT02290336T
Other languages
English (en)
Inventor
Sylvie Lesmanne
Christian Bernard
Pamphile Koumou
Original Assignee
Bull Sas
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull Sas filed Critical Bull Sas
Application granted granted Critical
Publication of ATE508412T1 publication Critical patent/ATE508412T1/de

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Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • G06F12/0817Cache consistency protocols using directory methods
    • G06F12/082Associative directories
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • G06F12/0831Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • G06F12/0817Cache consistency protocols using directory methods
    • G06F12/0826Limited pointers directories; State-only directories without pointers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Exchange Systems With Centralized Control (AREA)
AT02290336T 2001-02-15 2002-02-12 Kohärenzsteuerungsvorrichtung für eine mehrprozessorvorrichtung, modul und multimodularchitektur-mehrprozessorvorrichtung mit einer derartigen steuervorrichtung ATE508412T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0102089A FR2820850B1 (fr) 2001-02-15 2001-02-15 Controleur de coherence pour ensemble multiprocesseur, module et ensemble multiprocesseur a architecture multimodule integrant un tel controleur

Publications (1)

Publication Number Publication Date
ATE508412T1 true ATE508412T1 (de) 2011-05-15

Family

ID=8860073

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02290336T ATE508412T1 (de) 2001-02-15 2002-02-12 Kohärenzsteuerungsvorrichtung für eine mehrprozessorvorrichtung, modul und multimodularchitektur-mehrprozessorvorrichtung mit einer derartigen steuervorrichtung

Country Status (6)

Country Link
US (1) US7017011B2 (de)
EP (1) EP1233342B1 (de)
JP (1) JP2002304328A (de)
AT (1) ATE508412T1 (de)
DE (1) DE60239906D1 (de)
FR (1) FR2820850B1 (de)

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Also Published As

Publication number Publication date
JP2002304328A (ja) 2002-10-18
US7017011B2 (en) 2006-03-21
EP1233342B1 (de) 2011-05-04
FR2820850A1 (fr) 2002-08-16
FR2820850B1 (fr) 2003-05-09
DE60239906D1 (de) 2011-06-16
US20020112132A1 (en) 2002-08-15
EP1233342A1 (de) 2002-08-21

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