ATE521085T1 - Verfahren zum herstellen einer halbleiter-auf- isolation-heterostruktur - Google Patents

Verfahren zum herstellen einer halbleiter-auf- isolation-heterostruktur

Info

Publication number
ATE521085T1
ATE521085T1 AT06793255T AT06793255T ATE521085T1 AT E521085 T1 ATE521085 T1 AT E521085T1 AT 06793255 T AT06793255 T AT 06793255T AT 06793255 T AT06793255 T AT 06793255T AT E521085 T1 ATE521085 T1 AT E521085T1
Authority
AT
Austria
Prior art keywords
heterostructure
semiconductor
insulating layer
active layer
bonding
Prior art date
Application number
AT06793255T
Other languages
English (en)
Inventor
Xavier Hebras
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE521085T1 publication Critical patent/ATE521085T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/974—Substrate surface preparation

Landscapes

  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Formation Of Insulating Films (AREA)
  • Bipolar Transistors (AREA)
  • Light Receiving Elements (AREA)
  • Semiconductor Lasers (AREA)
AT06793255T 2005-09-08 2006-09-06 Verfahren zum herstellen einer halbleiter-auf- isolation-heterostruktur ATE521085T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0509168A FR2890489B1 (fr) 2005-09-08 2005-09-08 Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant
PCT/EP2006/066046 WO2007028800A1 (fr) 2005-09-08 2006-09-06 Procédé de fabrication d'une hétérostructure de type semi-conducteur sur isolant

Publications (1)

Publication Number Publication Date
ATE521085T1 true ATE521085T1 (de) 2011-09-15

Family

ID=36593036

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06793255T ATE521085T1 (de) 2005-09-08 2006-09-06 Verfahren zum herstellen einer halbleiter-auf- isolation-heterostruktur

Country Status (8)

Country Link
US (1) US7485551B2 (de)
EP (1) EP1922751B1 (de)
JP (1) JP2009508329A (de)
KR (1) KR100979930B1 (de)
CN (1) CN101258591B (de)
AT (1) ATE521085T1 (de)
FR (1) FR2890489B1 (de)
WO (1) WO2007028800A1 (de)

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008270706A (ja) * 2007-03-26 2008-11-06 Tokyo Electron Ltd 窒化珪素膜および不揮発性半導体メモリ装置
FR2919427B1 (fr) * 2007-07-26 2010-12-03 Soitec Silicon On Insulator Structure a reservoir de charges.
FR2926674B1 (fr) 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable
WO2009112894A1 (en) * 2008-03-13 2009-09-17 S.O.I.Tec Silicon On Insulator Technologies Substrate having a charged zone in an insulating buried layer
FR2934925B1 (fr) * 2008-08-06 2011-02-25 Soitec Silicon On Insulator Procede de fabrication d'une structure comprernant une etape d'implantations d'ions pour stabiliser l'interface de collage.
EP2157602A1 (de) * 2008-08-20 2010-02-24 Max-Planck-Gesellschaft zur Förderung der Wissenschaften e.V. Verfahren zur Herstellung einer Vielzahl von Herstellungs-Wafern
JP5470839B2 (ja) * 2008-12-25 2014-04-16 株式会社Ｓｕｍｃｏ 貼り合わせシリコンウェーハの製造方法
WO2011011764A2 (en) * 2009-07-23 2011-01-27 Gigasi Solar, Inc. Systems, methods and materials involving crystallization of substrates using a seed layer, as well as products produced by such processes
WO2011017179A2 (en) 2009-07-28 2011-02-10 Gigasi Solar, Inc. Systems, methods and materials including crystallization of substrates via sub-melt laser anneal, as well as products produced by such processes
US8629436B2 (en) * 2009-08-14 2014-01-14 Gigasi Solar, Inc. Backside only contact thin-film solar cells and devices, systems and methods of fabricating same, and products produced by processes thereof
WO2011096326A1 (ja) * 2010-02-04 2011-08-11 富士電機システムズ株式会社 半導体素子の製造方法および半導体素子の製造装置
US8288811B2 (en) 2010-03-22 2012-10-16 Micron Technology, Inc. Fortification of charge-storing material in high-K dielectric environments and resulting apparatuses
US20110306180A1 (en) * 2010-06-14 2011-12-15 Venkatraman Prabhakar Systems, Methods and Products Involving Aspects of Laser Irradiation, Cleaving, and/or Bonding Silicon-Containing Material to Substrates
FR2968121B1 (fr) * 2010-11-30 2012-12-21 Soitec Silicon On Insulator Procede de transfert d'une couche a haute temperature
FR2983342B1 (fr) 2011-11-30 2016-05-20 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure limitant la formation de defauts et heterostructure ainsi obtenue
FR3007891B1 (fr) * 2013-06-28 2016-11-25 Soitec Silicon On Insulator Procede de fabrication d'une structure composite
US8951896B2 (en) 2013-06-28 2015-02-10 International Business Machines Corporation High linearity SOI wafer for low-distortion circuit applications
WO2015112308A1 (en) 2014-01-23 2015-07-30 Sunedison Semiconductor Limited High resistivity soi wafers and a method of manufacturing thereof
EP3168862B1 (de) * 2014-07-10 2022-07-06 Sicoxs Corporation Halbleitersubstrat und halbleitersubstratherstellungsverfahren
US9899499B2 (en) 2014-09-04 2018-02-20 Sunedison Semiconductor Limited (Uen201334164H) High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss
EP3221885B1 (de) 2014-11-18 2019-10-23 GlobalWafers Co., Ltd. Hochresistiver halbleiter-auf-isolator-wafer und verfahren zur herstellung
US10224233B2 (en) 2014-11-18 2019-03-05 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He-N2 co-implantation
US10381260B2 (en) 2014-11-18 2019-08-13 GlobalWafers Co., Inc. Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers
JP6517360B2 (ja) 2015-03-03 2019-05-22 サンエディソン・セミコンダクター・リミテッドＳｕｎＥｄｉｓｏｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｌｉｍｉｔｅｄ 膜応力を制御可能なシリコン基板の上に電荷トラップ用多結晶シリコン膜を成長させる方法
US9881832B2 (en) 2015-03-17 2018-01-30 Sunedison Semiconductor Limited (Uen201334164H) Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof
JP6637515B2 (ja) 2015-03-17 2020-01-29 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． 半導体オン・インシュレータ構造の製造において使用するための熱的に安定した電荷トラップ層
CN106158639B (zh) * 2015-04-01 2019-01-29 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
CN114496732B (zh) 2015-06-01 2023-03-03 环球晶圆股份有限公司 制造绝缘体上硅锗的方法
WO2016196060A1 (en) 2015-06-01 2016-12-08 Sunedison Semiconductor Limited A method of manufacturing semiconductor-on-insulator
EP3378094B1 (de) 2015-11-20 2021-09-15 Globalwafers Co., Ltd. Herstellungsverfahren zum glätten einer halbleiteroberfläche
US9831115B2 (en) 2016-02-19 2017-11-28 Sunedison Semiconductor Limited (Uen201334164H) Process flow for manufacturing semiconductor on insulator structures in parallel
US10622247B2 (en) 2016-02-19 2020-04-14 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a buried high resistivity layer
WO2017142704A1 (en) 2016-02-19 2017-08-24 Sunedison Semiconductor Limited High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface
US10573550B2 (en) 2016-03-07 2020-02-25 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof
WO2017155808A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof
WO2017155804A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment
EP3758050A1 (de) 2016-03-07 2020-12-30 GlobalWafers Co., Ltd. Halbleiter-auf-isolator-struktur mit niedrigtemperatur-fliessfähiger oxidschicht und verfahren zur herstellung davon
FR3051785B1 (fr) * 2016-05-25 2025-04-25 Soitec Silicon On Insulator Procede de fabrication d'une couche
EP3995608A1 (de) 2016-06-08 2022-05-11 GlobalWafers Co., Ltd. Hochohmige monokristalline siliciumbarren und wafer mit verbesserter mechanischer festigkeit
US10269617B2 (en) 2016-06-22 2019-04-23 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising an isolation region
US20180019169A1 (en) * 2016-07-12 2018-01-18 QMAT, Inc. Backing substrate stabilizing donor substrate for implant or reclamation
US20180033609A1 (en) * 2016-07-28 2018-02-01 QMAT, Inc. Removal of non-cleaved/non-transferred material from donor substrate
JP6831911B2 (ja) 2016-10-26 2021-02-17 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． 向上した電荷捕獲効率を有する高抵抗率シリコンオンインシュレータ基板
JP6801105B2 (ja) 2016-12-05 2020-12-16 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． 高抵抗シリコンオンインシュレータ構造及びその製造方法
CN106683980B (zh) * 2016-12-27 2019-12-13 上海新傲科技股份有限公司 带有载流子俘获中心的衬底的制备方法
CN106783725B (zh) * 2016-12-27 2019-09-17 上海新傲科技股份有限公司 带有绝缘埋层的衬底的制备方法
EP3562978B1 (de) 2016-12-28 2021-03-10 Sunedison Semiconductor Limited Verfahren zur behandlung von siliciumwafern mit intrinsischer getterungs- und gate-oxid-integritäts-ausbeute
JP7034186B2 (ja) 2017-07-14 2022-03-11 サンエディソン・セミコンダクター・リミテッド 絶縁体上半導体構造の製造方法
JP7160943B2 (ja) 2018-04-27 2022-10-25 グローバルウェーハズ カンパニー リミテッド 半導体ドナー基板からの層移転を容易にする光アシスト板状体形成
CN112262467B (zh) 2018-06-08 2024-08-09 环球晶圆股份有限公司 将硅薄层移转的方法
CN110880920B (zh) * 2018-09-06 2021-01-19 中国科学院上海微系统与信息技术研究所 异质薄膜结构的制备方法
FR3091000B1 (fr) 2018-12-24 2020-12-04 Soitec Silicon On Insulator Procede de fabrication d’un substrat pour un capteur d’image de type face avant
FR3111232B1 (fr) * 2020-06-09 2022-05-06 Soitec Silicon On Insulator Substrat temporaire demontable compatible avec de tres hautes temperatures et procede de transfert d’une couche utile a partir dudit substrat

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3217089B2 (ja) * 1991-08-23 2001-10-09 富士通株式会社 Ｓｏｉウェハおよびその製造方法
JPH05226666A (ja) * 1992-02-13 1993-09-03 Kawasaki Steel Corp 半導体装置の製造方法
JPH05259012A (ja) * 1992-03-10 1993-10-08 Nec Corp 半導体基板およびその製造方法
JP3192000B2 (ja) * 1992-08-25 2001-07-23 キヤノン株式会社 半導体基板及びその作製方法
JPH0964205A (ja) * 1995-08-22 1997-03-07 Sony Corp 窒化シリコン膜の形成方法
KR100232886B1 (ko) * 1996-11-23 1999-12-01 김영환 Soi 웨이퍼 제조방법
US6159824A (en) * 1997-05-12 2000-12-12 Silicon Genesis Corporation Silicon-on-silicon wafer bonding process using a thin film blister-separation method
JP3975634B2 (ja) * 2000-01-25 2007-09-12 信越半導体株式会社 半導体ウェハの製作法
CA2482258A1 (en) * 2001-04-17 2002-10-24 California Institute Of Technology A method of using a germanium layer transfer to si for photovoltaic applications and heterostructure made thereby
US20020187619A1 (en) * 2001-05-04 2002-12-12 International Business Machines Corporation Gettering process for bonded SOI wafers
US6696352B1 (en) * 2001-09-11 2004-02-24 Silicon Wafer Technologies, Inc. Method of manufacture of a multi-layered substrate with a thin single crystalline layer and a versatile sacrificial layer
CN1172376C (zh) * 2001-12-29 2004-10-20 中国科学院上海微系统与信息技术研究所 一种类似绝缘层上硅结构的材料及制备方法
US6979630B2 (en) * 2002-08-08 2005-12-27 Isonics Corporation Method and apparatus for transferring a thin layer of semiconductor material
JP2004087768A (ja) * 2002-08-27 2004-03-18 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法
WO2004021420A2 (en) * 2002-08-29 2004-03-11 Massachusetts Institute Of Technology Fabrication method for a monocrystalline semiconductor layer on a substrate
FR2845523B1 (fr) * 2002-10-07 2005-10-28 Procede pour realiser un substrat par transfert d'une plaquette donneuse comportant des especes etrangeres, et plaquette donneuse associee
US7052978B2 (en) * 2003-08-28 2006-05-30 Intel Corporation Arrangements incorporating laser-induced cleaving
JPWO2005022610A1 (ja) * 2003-09-01 2007-11-01 株式会社Sumco 貼り合わせウェーハの製造方法
US6972247B2 (en) * 2003-12-05 2005-12-06 International Business Machines Corporation Method of fabricating strained Si SOI wafers
FR2865574B1 (fr) * 2004-01-26 2006-04-07 Soitec Silicon On Insulator Procede de fabrication d'un substrat demontable
US7919391B2 (en) * 2004-12-24 2011-04-05 S.O.I.Tec Silicon On Insulator Technologies Methods for preparing a bonding surface of a semiconductor wafer
US7344957B2 (en) * 2005-01-19 2008-03-18 Texas Instruments Incorporated SOI wafer with cooling channels and a method of manufacture thereof

Also Published As

Publication number Publication date
CN101258591B (zh) 2011-04-20
JP2009508329A (ja) 2009-02-26
FR2890489A1 (fr) 2007-03-09
EP1922751A1 (de) 2008-05-21
FR2890489B1 (fr) 2008-03-07
EP1922751B1 (de) 2011-08-17
WO2007028800A1 (fr) 2007-03-15
US20070054466A1 (en) 2007-03-08
CN101258591A (zh) 2008-09-03
US7485551B2 (en) 2009-02-03
KR100979930B1 (ko) 2010-09-03
KR20080040759A (ko) 2008-05-08

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