ATE521085T1 - Verfahren zum herstellen einer halbleiter-auf- isolation-heterostruktur - Google Patents

Verfahren zum herstellen einer halbleiter-auf- isolation-heterostruktur

Info

Publication number
ATE521085T1
ATE521085T1 AT06793255T AT06793255T ATE521085T1 AT E521085 T1 ATE521085 T1 AT E521085T1 AT 06793255 T AT06793255 T AT 06793255T AT 06793255 T AT06793255 T AT 06793255T AT E521085 T1 ATE521085 T1 AT E521085T1
Authority
AT
Austria
Prior art keywords
heterostructure
semiconductor
insulating layer
active layer
bonding
Prior art date
Application number
AT06793255T
Other languages
English (en)
Inventor
Xavier Hebras
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE521085T1 publication Critical patent/ATE521085T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/974—Substrate surface preparation

Landscapes

  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Semiconductor Lasers (AREA)
  • Bipolar Transistors (AREA)
  • Light Receiving Elements (AREA)
  • Formation Of Insulating Films (AREA)
AT06793255T 2005-09-08 2006-09-06 Verfahren zum herstellen einer halbleiter-auf- isolation-heterostruktur ATE521085T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0509168A FR2890489B1 (fr) 2005-09-08 2005-09-08 Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant
PCT/EP2006/066046 WO2007028800A1 (fr) 2005-09-08 2006-09-06 Procédé de fabrication d'une hétérostructure de type semi-conducteur sur isolant

Publications (1)

Publication Number Publication Date
ATE521085T1 true ATE521085T1 (de) 2011-09-15

Family

ID=36593036

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06793255T ATE521085T1 (de) 2005-09-08 2006-09-06 Verfahren zum herstellen einer halbleiter-auf- isolation-heterostruktur

Country Status (8)

Country Link
US (1) US7485551B2 (de)
EP (1) EP1922751B1 (de)
JP (1) JP2009508329A (de)
KR (1) KR100979930B1 (de)
CN (1) CN101258591B (de)
AT (1) ATE521085T1 (de)
FR (1) FR2890489B1 (de)
WO (1) WO2007028800A1 (de)

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Also Published As

Publication number Publication date
FR2890489A1 (fr) 2007-03-09
US7485551B2 (en) 2009-02-03
EP1922751B1 (de) 2011-08-17
CN101258591B (zh) 2011-04-20
KR20080040759A (ko) 2008-05-08
KR100979930B1 (ko) 2010-09-03
CN101258591A (zh) 2008-09-03
JP2009508329A (ja) 2009-02-26
US20070054466A1 (en) 2007-03-08
WO2007028800A1 (fr) 2007-03-15
FR2890489B1 (fr) 2008-03-07
EP1922751A1 (de) 2008-05-21

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