ATE522869T1 - System mit prozessor und eingabe-ausgabe- steuerung - Google Patents

System mit prozessor und eingabe-ausgabe- steuerung

Info

Publication number
ATE522869T1
ATE522869T1 AT09173661T AT09173661T ATE522869T1 AT E522869 T1 ATE522869 T1 AT E522869T1 AT 09173661 T AT09173661 T AT 09173661T AT 09173661 T AT09173661 T AT 09173661T AT E522869 T1 ATE522869 T1 AT E522869T1
Authority
AT
Austria
Prior art keywords
processor
execution
request
controller
requests
Prior art date
Application number
AT09173661T
Other languages
English (en)
Inventor
Souta Kusachi
Go Sugizaki
Satoshi Nakagawa
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of ATE522869T1 publication Critical patent/ATE522869T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
  • Hardware Redundancy (AREA)
AT09173661T 2008-11-14 2009-10-21 System mit prozessor und eingabe-ausgabe- steuerung ATE522869T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008292721A JP5239769B2 (ja) 2008-11-14 2008-11-14 リクエスト順序制御システム、リクエスト順序制御方法およびリクエスト順序制御プログラム

Publications (1)

Publication Number Publication Date
ATE522869T1 true ATE522869T1 (de) 2011-09-15

Family

ID=42035576

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09173661T ATE522869T1 (de) 2008-11-14 2009-10-21 System mit prozessor und eingabe-ausgabe- steuerung

Country Status (6)

Country Link
US (1) US8185668B2 (de)
EP (1) EP2189911B1 (de)
JP (1) JP5239769B2 (de)
KR (1) KR101087177B1 (de)
CN (1) CN101739341B (de)
AT (1) ATE522869T1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8392621B2 (en) * 2010-06-22 2013-03-05 International Business Machines Corporation Managing dataflow in a temporary memory
US9342393B2 (en) 2011-12-30 2016-05-17 Intel Corporation Early fabric error forwarding
US9134919B2 (en) 2012-03-29 2015-09-15 Samsung Electronics Co., Ltd. Memory device including priority information and method of operating the same

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61250748A (ja) * 1985-04-27 1986-11-07 Nec Eng Ltd 情報処理装置のメモリアクセス方式
JPH04190435A (ja) * 1990-11-26 1992-07-08 Hitachi Ltd マルチプロセッサシステムのメモリアクセス順序保証方式
JPH06187231A (ja) * 1992-12-22 1994-07-08 Hitachi Ltd 計算機システム
US6167492A (en) * 1998-12-23 2000-12-26 Advanced Micro Devices, Inc. Circuit and method for maintaining order of memory access requests initiated by devices coupled to a multiprocessor system
US6275913B1 (en) * 1999-10-15 2001-08-14 Micron Technology, Inc. Method for preserving memory request ordering across multiple memory controllers
US6681320B1 (en) * 1999-12-29 2004-01-20 Intel Corporation Causality-based memory ordering in a multiprocessing environment
TW515960B (en) * 2000-08-11 2003-01-01 Via Tech Inc Architecture and method of extended bus and bridge thereof
JP4463276B2 (ja) * 2004-07-02 2010-05-19 日本電気株式会社 マルチプロセッサシステムおよびメモリアクセス処理方法
JP4305378B2 (ja) * 2004-12-13 2009-07-29 ソニー株式会社 データ処理システム、アクセス制御方法、その装置およびそのプログラム
JP2006260140A (ja) * 2005-03-17 2006-09-28 Fujitsu Ltd データ処理システム
JP4463190B2 (ja) * 2005-11-24 2010-05-12 エヌイーシーコンピュータテクノ株式会社 マルチプロセッサシステム及び入出力制御装置並びにリクエスト発行方法
WO2007097017A1 (ja) * 2006-02-27 2007-08-30 Fujitsu Limited バッファリング装置およびバッファリング方法
US7917676B2 (en) * 2006-03-10 2011-03-29 Qualcomm, Incorporated Efficient execution of memory barrier bus commands with order constrained memory accesses

Also Published As

Publication number Publication date
CN101739341A (zh) 2010-06-16
US8185668B2 (en) 2012-05-22
JP2010118020A (ja) 2010-05-27
KR20100054734A (ko) 2010-05-25
CN101739341B (zh) 2013-10-16
JP5239769B2 (ja) 2013-07-17
KR101087177B1 (ko) 2011-11-25
US20100125687A1 (en) 2010-05-20
EP2189911B1 (de) 2011-08-31
EP2189911A1 (de) 2010-05-26

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Legal Events

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