ATE524577T1 - Verfahren zur herstellung einer epitaktisch aufgewachsenen schicht - Google Patents

Verfahren zur herstellung einer epitaktisch aufgewachsenen schicht

Info

Publication number
ATE524577T1
ATE524577T1 AT04763149T AT04763149T ATE524577T1 AT E524577 T1 ATE524577 T1 AT E524577T1 AT 04763149 T AT04763149 T AT 04763149T AT 04763149 T AT04763149 T AT 04763149T AT E524577 T1 ATE524577 T1 AT E524577T1
Authority
AT
Austria
Prior art keywords
layer
producing
substrate
grown layer
epitactically grown
Prior art date
Application number
AT04763149T
Other languages
English (en)
Inventor
Bruce Faure
Cioccio Lea Di
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE524577T1 publication Critical patent/ATE524577T1/de

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/22—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement by transferring layers from a donor substrate to a final substrate utilising a temporary handle substrate as an intermediary
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
AT04763149T 2003-07-24 2004-07-07 Verfahren zur herstellung einer epitaktisch aufgewachsenen schicht ATE524577T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0309076A FR2857982B1 (fr) 2003-07-24 2003-07-24 Procede de fabrication d'une couche epitaxiee
PCT/EP2004/007577 WO2005014895A1 (en) 2003-07-24 2004-07-07 A method of fabricating an epitaxially grown layer

Publications (1)

Publication Number Publication Date
ATE524577T1 true ATE524577T1 (de) 2011-09-15

Family

ID=33561068

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04763149T ATE524577T1 (de) 2003-07-24 2004-07-07 Verfahren zur herstellung einer epitaktisch aufgewachsenen schicht

Country Status (8)

Country Link
EP (1) EP1664396B1 (de)
JP (1) JP5031364B2 (de)
KR (1) KR100798976B1 (de)
CN (1) CN100415947C (de)
AT (1) ATE524577T1 (de)
FR (1) FR2857982B1 (de)
TW (1) TWI278540B (de)
WO (1) WO2005014895A1 (de)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7538010B2 (en) 2003-07-24 2009-05-26 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating an epitaxially grown layer
FR2857983B1 (fr) 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
US7417266B1 (en) 2004-06-10 2008-08-26 Qspeed Semiconductor Inc. MOSFET having a JFET embedded as a body diode
TW200707799A (en) * 2005-04-21 2007-02-16 Aonex Technologies Inc Bonded intermediate substrate and method of making same
FR2888402B1 (fr) * 2005-07-06 2007-12-21 Commissariat Energie Atomique Procede d'assemblage de substrats par depot d'une couche mince de collage d'oxyde ou de nitrure et structure ainsi assemblee
FR2888663B1 (fr) 2005-07-13 2008-04-18 Soitec Silicon On Insulator Procede de diminution de la rugosite d'une couche epaisse d'isolant
FR2896619B1 (fr) * 2006-01-23 2008-05-23 Soitec Silicon On Insulator Procede de fabrication d'un substrat composite a proprietes electriques ameliorees
FR2896618B1 (fr) 2006-01-23 2008-05-23 Soitec Silicon On Insulator Procede de fabrication d'un substrat composite
EP1835533B1 (de) 2006-03-14 2020-06-03 Soitec Verfahren zum Herstellen von zusammengesetzten Hableiterscheiben und Verfahren zur Wiederverwendung des gebrauchten Substrats
FR2899378B1 (fr) * 2006-03-29 2008-06-27 Commissariat Energie Atomique Procede de detachement d'un film mince par fusion de precipites
FR2917232B1 (fr) * 2007-06-06 2009-10-09 Soitec Silicon On Insulator Procede de fabrication d'une structure pour epitaxie sans zone d'exclusion.
FR2926672B1 (fr) 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication de couches de materiau epitaxie
FR2926674B1 (fr) 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable
TWI496189B (zh) * 2008-12-23 2015-08-11 Siltectra Gmbh 製造具結構表面之固態材料之薄獨立層的方法
NL2003250C2 (en) * 2009-07-20 2011-01-24 Metal Membranes Com B V Method for producing a membrane and such membrane.
FR2967813B1 (fr) * 2010-11-18 2013-10-04 Soitec Silicon On Insulator Procédé de réalisation d'une structure a couche métallique enterrée
TWI449224B (zh) * 2011-02-25 2014-08-11 Univ Nat Chiao Tung 半導體發光元件
JP5704602B2 (ja) * 2011-03-17 2015-04-22 リンテック株式会社 薄型半導体装置の製造方法および脆質部材用支持体
RU2469433C1 (ru) * 2011-07-13 2012-12-10 Юрий Георгиевич Шретер Способ лазерного отделения эпитаксиальной пленки или слоя эпитаксиальной пленки от ростовой подложки эпитаксиальной полупроводниковой структуры (варианты)
US8633094B2 (en) 2011-12-01 2014-01-21 Power Integrations, Inc. GaN high voltage HFET with passivation plus gate dielectric multilayer structure
US8940620B2 (en) 2011-12-15 2015-01-27 Power Integrations, Inc. Composite wafer for fabrication of semiconductor devices
CN102560676B (zh) * 2012-01-18 2014-08-06 山东大学 一种使用减薄键合结构进行GaN单晶生长的方法
TWI474381B (zh) * 2012-08-17 2015-02-21 Nat Univ Chung Hsing Preparation method of epitaxial substrate
CN103074672A (zh) * 2013-01-06 2013-05-01 向勇 一种单晶硅的气相外延生长方法
US8928037B2 (en) 2013-02-28 2015-01-06 Power Integrations, Inc. Heterostructure power transistor with AlSiN passivation layer
CN103545239B (zh) * 2013-09-17 2017-01-11 新磊半导体科技（苏州）有限公司 一种基于薄膜型的外延片剥离工艺
KR101578717B1 (ko) * 2014-05-20 2015-12-22 주식회사 루미스탈 질화갈륨 웨이퍼를 제조하는 방법
FR3036224B1 (fr) * 2015-05-13 2017-06-02 Commissariat Energie Atomique Procede de collage direct
KR20180010274A (ko) * 2015-06-19 2018-01-30 큐맷, 인코포레이티드 본드 및 릴리스 레이어 이송 프로세스
EP3451203A1 (de) * 2017-08-30 2019-03-06 Dassault Systèmes Computerimplementiertes verfahren zur berechnung einer hülle für ein gebäude mit einhaltung von schattendaueranforderungen
CN108010834A (zh) * 2017-11-22 2018-05-08 电子科技大学 一种柔性单晶薄膜及其制备与转移方法
FR3079532B1 (fr) 2018-03-28 2022-03-25 Soitec Silicon On Insulator Procede de fabrication d'une couche monocristalline de materiau ain et substrat pour croissance par epitaxie d'une couche monocristalline de materiau ain
JP7204625B2 (ja) * 2019-07-25 2023-01-16 信越化学工業株式会社 Ｉｉｉ族化合物基板の製造方法及びその製造方法により製造した基板
WO2021014834A1 (ja) * 2019-07-25 2021-01-28 信越化学工業株式会社 Ｉｉｉ族化合物基板の製造方法及びその製造方法により製造した基板
FR3108439B1 (fr) * 2020-03-23 2022-02-11 Soitec Silicon On Insulator Procede de fabrication d’une structure empilee
FR3108775B1 (fr) * 2020-03-27 2022-02-18 Soitec Silicon On Insulator Procede de fabrication d’une structure composite comprenant une couche mince en sic monocristallin sur un substrat support en sic
FR3108774B1 (fr) * 2020-03-27 2022-02-18 Soitec Silicon On Insulator Procede de fabrication d’une structure composite comprenant une couche mince en sic monocristallin sur un substrat support en sic
TWI896630B (zh) * 2020-04-14 2025-09-11 學校法人關西學院 氮化鋁基板的製造方法、氮化鋁基板以及氮化鋁層中的裂痕產生的抑制方法
CN113555277A (zh) * 2020-04-23 2021-10-26 无锡华润上华科技有限公司 碳化硅器件及其制备方法
FR3114912B1 (fr) * 2020-10-06 2022-09-02 Soitec Silicon On Insulator Procédé de fabrication d’un substrat pour la croissance épitaxiale d’une couche d’un alliage III-N à base de gallium
FR3114909B1 (fr) * 2020-10-06 2023-03-17 Soitec Silicon On Insulator Procédé de fabrication d’un substrat pour la croissance épitaxiale d’une couche d’un alliage III-N à base de gallium
WO2025062300A1 (en) * 2023-09-22 2025-03-27 Silanna UV Technologies Pte Ltd Semiconductor device with layer transfer
US12453109B2 (en) 2023-09-22 2025-10-21 Silanna UV Technologies Pte Ltd Semiconductor device
CN117690943B (zh) * 2024-01-31 2024-06-04 合肥晶合集成电路股份有限公司 一种图像传感器的制作方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10223496A (ja) * 1997-02-12 1998-08-21 Ion Kogaku Kenkyusho:Kk 単結晶ウエハおよびその製造方法
WO1999001594A1 (en) * 1997-07-03 1999-01-14 Cbl Technologies Thermal mismatch compensation to produce free standing substrates by epitaxial deposition
FR2767416B1 (fr) * 1997-08-12 1999-10-01 Commissariat Energie Atomique Procede de fabrication d'un film mince de materiau solide
FR2774214B1 (fr) * 1998-01-28 2002-02-08 Commissariat Energie Atomique PROCEDE DE REALISATION D'UNE STRUCTURE DE TYPE SEMI-CONDUCTEUR SUR ISOLANT ET EN PARTICULIER SiCOI
US6335263B1 (en) * 2000-03-22 2002-01-01 The Regents Of The University Of California Method of forming a low temperature metal bond for use in the transfer of bulk and thin film materials
FR2807074B1 (fr) * 2000-04-03 2002-12-06 Soitec Silicon On Insulator Procede et dispositif de fabrication de substrats
FR2817394B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
FR2817395B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
JP3729065B2 (ja) * 2000-12-05 2005-12-21 日立電線株式会社 窒化物半導体エピタキシャルウェハの製造方法及び窒化物半導体エピタキシャルウェハ
JP4127463B2 (ja) * 2001-02-14 2008-07-30 豊田合成株式会社 Ｉｉｉ族窒化物系化合物半導体の結晶成長方法及びｉｉｉ族窒化物系化合物半導体発光素子の製造方法
JP4633962B2 (ja) * 2001-05-18 2011-02-16 日亜化学工業株式会社 窒化物半導体基板の製造方法
JP2003068654A (ja) * 2001-08-27 2003-03-07 Hoya Corp 化合物単結晶の製造方法
JP2003095798A (ja) * 2001-09-27 2003-04-03 Hoya Corp 単結晶基板の製造方法
KR101072433B1 (ko) * 2005-03-21 2011-10-11 삼성코닝정밀소재 주식회사 질화물계 반도체 단결정 기판의 제조방법

Also Published As

Publication number Publication date
JP2006528592A (ja) 2006-12-21
KR20060036472A (ko) 2006-04-28
TWI278540B (en) 2007-04-11
KR100798976B1 (ko) 2008-01-28
FR2857982B1 (fr) 2007-05-18
EP1664396A1 (de) 2006-06-07
JP5031364B2 (ja) 2012-09-19
FR2857982A1 (fr) 2005-01-28
TW200517532A (en) 2005-06-01
CN100415947C (zh) 2008-09-03
CN1826434A (zh) 2006-08-30
EP1664396B1 (de) 2011-09-14
WO2005014895A1 (en) 2005-02-17

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