ATE520149T1 - Verfahren zur herstellung eines epitaktischen substrats - Google Patents

Verfahren zur herstellung eines epitaktischen substrats

Info

Publication number
ATE520149T1
ATE520149T1 AT04739271T AT04739271T ATE520149T1 AT E520149 T1 ATE520149 T1 AT E520149T1 AT 04739271 T AT04739271 T AT 04739271T AT 04739271 T AT04739271 T AT 04739271T AT E520149 T1 ATE520149 T1 AT E520149T1
Authority
AT
Austria
Prior art keywords
substrate
base substrate
epitactic
producing
preparation
Prior art date
Application number
AT04739271T
Other languages
English (en)
Inventor
Bruce Faure
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE520149T1 publication Critical patent/ATE520149T1/de

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/183—Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/915—Separating from substrate

Landscapes

  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
AT04739271T 2003-06-06 2004-05-19 Verfahren zur herstellung eines epitaktischen substrats ATE520149T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03291371A EP1484794A1 (de) 2003-06-06 2003-06-06 Verfahren zur Herstellung eines Trägersubstrats
PCT/EP2004/005439 WO2004112126A1 (en) 2003-06-06 2004-05-19 A method of preparation of an epitaxial substrate

Publications (1)

Publication Number Publication Date
ATE520149T1 true ATE520149T1 (de) 2011-08-15

Family

ID=33155276

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04739271T ATE520149T1 (de) 2003-06-06 2004-05-19 Verfahren zur herstellung eines epitaktischen substrats

Country Status (8)

Country Link
US (1) US7226509B2 (de)
EP (2) EP1484794A1 (de)
JP (1) JP4733633B2 (de)
KR (1) KR100746179B1 (de)
CN (1) CN100576503C (de)
AT (1) ATE520149T1 (de)
TW (1) TWI269371B (de)
WO (1) WO2004112126A1 (de)

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FR2855910B1 (fr) * 2003-06-06 2005-07-15 Commissariat Energie Atomique Procede d'obtention d'une couche tres mince par amincissement par auto-portage provoque
FR2857983B1 (fr) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
US7538010B2 (en) * 2003-07-24 2009-05-26 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating an epitaxially grown layer
TWI415288B (zh) * 2005-03-22 2013-11-11 住友化學股份有限公司 獨立基板、其製造方法，以及半導體發光元件
CN101378008B (zh) * 2008-09-19 2010-06-02 苏州纳维科技有限公司 分离外延层与衬底的方法
FR2936903B1 (fr) * 2008-10-07 2011-01-14 Soitec Silicon On Insulator Relaxation d'une couche de materiau contraint avec application d'un raidisseur
US9142412B2 (en) 2011-02-03 2015-09-22 Soitec Semiconductor devices including substrate layers and overlying semiconductor layers having closely matching coefficients of thermal expansion, and related methods
US8436363B2 (en) 2011-02-03 2013-05-07 Soitec Metallic carrier for layer transfer and methods for forming the same
US9082948B2 (en) 2011-02-03 2015-07-14 Soitec Methods of fabricating semiconductor structures using thermal spray processes, and semiconductor structures fabricated using such methods
RU2469433C1 (ru) * 2011-07-13 2012-12-10 Юрий Георгиевич Шретер Способ лазерного отделения эпитаксиальной пленки или слоя эпитаксиальной пленки от ростовой подложки эпитаксиальной полупроводниковой структуры (варианты)
US8541315B2 (en) * 2011-09-19 2013-09-24 International Business Machines Corporation High throughput epitaxial lift off for flexible electronics
CN102560676B (zh) * 2012-01-18 2014-08-06 山东大学 一种使用减薄键合结构进行GaN单晶生长的方法
JP2013247362A (ja) * 2012-05-29 2013-12-09 Samsung Corning Precision Materials Co Ltd 半導体素子用薄膜貼り合わせ基板の製造方法
JP2014192307A (ja) * 2013-03-27 2014-10-06 Disco Abrasive Syst Ltd サファイア基板の平坦加工方法
KR101485908B1 (ko) * 2013-05-16 2015-01-26 전북대학교산학협력단 고온 에피층을 이종 기판에 성장하는 구조 및 그 제조 방법
WO2015034118A1 (ko) * 2013-09-09 2015-03-12 Yoo Bong Young 실리콘 기판의 표면 박리 방법
JP6539959B2 (ja) * 2014-08-28 2019-07-10 株式会社Sumco エピタキシャルシリコンウェーハおよびその製造方法、ならびに、固体撮像素子の製造方法
DE112016005550T5 (de) * 2015-12-04 2018-08-16 Applied Materials, Inc. Verfahren und Lösungen zur Reinigung von Ingaas (Oder III-V) Substraten
CN105609408B (zh) * 2015-12-23 2018-11-16 上海华虹宏力半导体制造有限公司 半导体器件的形成方法
KR101852767B1 (ko) * 2016-05-25 2018-04-27 전북대학교산학협력단 템플레이트 에피 기판 및 이의 제조방법
CN107910402B (zh) * 2017-06-28 2020-07-17 超晶科技（北京）有限公司 一种铟镓砷红外探测器材料制备方法
RU2657674C1 (ru) * 2017-08-14 2018-06-14 Федеральное государственное бюджетное учреждение науки Институт общей и неорганической химии им. Н.С. Курнакова Российской академии наук (ИОНХ РАН) Способ получения гетероструктуры Mg(Fe1-xGax)2O4/Si со стабильной межфазной границей
KR102234101B1 (ko) 2018-09-21 2021-04-01 고려대학교 산학협력단 박막성장구조, 박막성장방법 및 박막열처리방법
FR3099637B1 (fr) * 2019-08-01 2021-07-09 Soitec Silicon On Insulator procédé de fabrication d’unE structure composite comprenant une couche mince en Sic monocristallin sur un substrat support en sic polycristallin
FR3103962B1 (fr) * 2019-11-29 2021-11-05 Soitec Silicon On Insulator Procede de fabrication d’une structure composite comprenant une couche mince en sic monocristallin sur un substrat support en sic cristallin
FR3108774B1 (fr) * 2020-03-27 2022-02-18 Soitec Silicon On Insulator Procede de fabrication d’une structure composite comprenant une couche mince en sic monocristallin sur un substrat support en sic
FR3111232B1 (fr) * 2020-06-09 2022-05-06 Soitec Silicon On Insulator Substrat temporaire demontable compatible avec de tres hautes temperatures et procede de transfert d’une couche utile a partir dudit substrat
CN112635323B (zh) * 2020-12-15 2021-12-28 中国科学院上海微系统与信息技术研究所 一种SiC基异质集成氮化镓薄膜与HEMT器件的制备方法
WO2025188114A1 (ko) * 2024-03-08 2025-09-12 웨이브로드 주식회사 핫 셀프스플릿 공정을 통한 고품질 그룹 3족 질화물 반도체를 위한 엔지니어드 성장기판 제작 방법

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Also Published As

Publication number Publication date
EP1631986A1 (de) 2006-03-08
KR100746179B1 (ko) 2007-08-03
US20040255846A1 (en) 2004-12-23
TW200501239A (en) 2005-01-01
EP1631986B1 (de) 2011-08-10
JP4733633B2 (ja) 2011-07-27
CN1802739A (zh) 2006-07-12
WO2004112126A1 (en) 2004-12-23
EP1484794A1 (de) 2004-12-08
US7226509B2 (en) 2007-06-05
TWI269371B (en) 2006-12-21
CN100576503C (zh) 2009-12-30
KR20060055462A (ko) 2006-05-23
JP2007524222A (ja) 2007-08-23

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