ATE528794T1 - Verfahren zur herstellung von lokalisierten geoi- strukturen, die durch germanium-anreicherung erhalten werden - Google Patents
Verfahren zur herstellung von lokalisierten geoi- strukturen, die durch germanium-anreicherung erhalten werdenInfo
- Publication number
- ATE528794T1 ATE528794T1 AT09168024T AT09168024T ATE528794T1 AT E528794 T1 ATE528794 T1 AT E528794T1 AT 09168024 T AT09168024 T AT 09168024T AT 09168024 T AT09168024 T AT 09168024T AT E528794 T1 ATE528794 T1 AT E528794T1
- Authority
- AT
- Austria
- Prior art keywords
- layer
- sige
- germanium
- silicon
- forming
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
- H10P14/665—Porous materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01356—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6302—Non-deposition formation processes
- H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
- H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
- H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6302—Non-deposition formation processes
- H10P14/6322—Formation by thermal treatments
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Landscapes
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
- Silicon Compounds (AREA)
- Silicates, Zeolites, And Molecular Sieves (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0855671A FR2935194B1 (fr) | 2008-08-22 | 2008-08-22 | Procede de realisation de structures geoi localisees, obtenues par enrichissement en germanium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE528794T1 true ATE528794T1 (de) | 2011-10-15 |
Family
ID=40451252
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT09168024T ATE528794T1 (de) | 2008-08-22 | 2009-08-18 | Verfahren zur herstellung von lokalisierten geoi- strukturen, die durch germanium-anreicherung erhalten werden |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9040391B2 (de) |
| EP (1) | EP2157603B1 (de) |
| JP (1) | JP2010050459A (de) |
| AT (1) | ATE528794T1 (de) |
| FR (1) | FR2935194B1 (de) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184940B (zh) | 2011-03-30 | 2014-01-08 | 清华大学 | 半导体结构及其形成方法 |
| JP2014187259A (ja) | 2013-03-25 | 2014-10-02 | Toshiba Corp | 半導体装置の製造方法 |
| US9406508B2 (en) * | 2013-10-31 | 2016-08-02 | Samsung Electronics Co., Ltd. | Methods of forming a semiconductor layer including germanium with low defectivity |
| CN104733320B (zh) * | 2013-12-24 | 2018-01-30 | 中芯国际集成电路制造(上海)有限公司 | 场效应晶体管及其制备方法 |
| FR3030882B1 (fr) | 2014-12-22 | 2018-03-09 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Circuit integre comportant des transistors pmos a tensions de seuil distinctes |
| US9698224B2 (en) | 2015-06-19 | 2017-07-04 | International Business Machines Corporation | Silicon germanium fin formation via condensation |
| US10600638B2 (en) | 2016-10-24 | 2020-03-24 | International Business Machines Corporation | Nanosheet transistors with sharp junctions |
| CN107359203A (zh) * | 2017-05-12 | 2017-11-17 | 惠科股份有限公司 | 显示面板和显示装置 |
| US10147820B1 (en) | 2017-07-26 | 2018-12-04 | International Business Machines Corporation | Germanium condensation for replacement metal gate devices with silicon germanium channel |
| US10690853B2 (en) | 2018-06-25 | 2020-06-23 | International Business Machines Corporation | Optoelectronics integration using semiconductor on insulator substrate |
| US10699967B2 (en) | 2018-06-28 | 2020-06-30 | International Business Machines Corporation | Co-integration of high carrier mobility PFET and NFET devices on the same substrate using low temperature condensation |
| FR3088481B1 (fr) * | 2018-11-14 | 2024-06-07 | Commissariat Energie Atomique | Procede de fabrication d’un transistor a effet de champ a jonction alignee avec des espaceurs |
| CN117672853A (zh) * | 2022-08-25 | 2024-03-08 | 上海华力集成电路制造有限公司 | SiGe沟道的形成方法 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3547419B2 (ja) * | 2001-03-13 | 2004-07-28 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US7125458B2 (en) * | 2003-09-12 | 2006-10-24 | International Business Machines Corporation | Formation of a silicon germanium-on-insulator structure by oxidation of a buried porous silicon layer |
| US20050221591A1 (en) * | 2004-04-06 | 2005-10-06 | International Business Machines Corporation | Method of forming high-quality relaxed SiGe alloy layers on bulk Si substrates |
| US7141115B2 (en) * | 2004-09-02 | 2006-11-28 | International Business Machines Corporation | Method of producing silicon-germanium-on-insulator material using unstrained Ge-containing source layers |
| US7550309B2 (en) * | 2004-09-24 | 2009-06-23 | Shin-Etsu Handotai Co., Ltd. | Method for producing semiconductor wafer |
| FR2898215B1 (fr) * | 2006-03-01 | 2008-05-16 | Commissariat Energie Atomique | Procede de fabrication d'un substrat par condensation germanium |
| FR2902234B1 (fr) | 2006-06-12 | 2008-10-10 | Commissariat Energie Atomique | PROCEDE DE REALISATION DE ZONES A BASE DE Si1-yGey DE DIFFERENTES TENEURS EN Ge SUR UN MEME SUBSTRAT PAR CONDENSATION DE GERMANIUM |
-
2008
- 2008-08-22 FR FR0855671A patent/FR2935194B1/fr not_active Expired - Fee Related
-
2009
- 2009-08-12 US US12/539,713 patent/US9040391B2/en active Active
- 2009-08-18 EP EP09168024A patent/EP2157603B1/de not_active Not-in-force
- 2009-08-18 AT AT09168024T patent/ATE528794T1/de not_active IP Right Cessation
- 2009-08-21 JP JP2009191900A patent/JP2010050459A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| FR2935194B1 (fr) | 2010-10-08 |
| EP2157603B1 (de) | 2011-10-12 |
| EP2157603A1 (de) | 2010-02-24 |
| JP2010050459A (ja) | 2010-03-04 |
| FR2935194A1 (fr) | 2010-02-26 |
| US9040391B2 (en) | 2015-05-26 |
| US20100044836A1 (en) | 2010-02-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |