ATE542297T1 - Computerprogramprodukt zum programmieren einer programmierbaren logischen schaltung mit redundanz, entsprechende anordnung und verfahren - Google Patents

Computerprogramprodukt zum programmieren einer programmierbaren logischen schaltung mit redundanz, entsprechende anordnung und verfahren

Info

Publication number
ATE542297T1
ATE542297T1 AT10180492T AT10180492T ATE542297T1 AT E542297 T1 ATE542297 T1 AT E542297T1 AT 10180492 T AT10180492 T AT 10180492T AT 10180492 T AT10180492 T AT 10180492T AT E542297 T1 ATE542297 T1 AT E542297T1
Authority
AT
Austria
Prior art keywords
computer program
program product
redundancy
programming
logical circuit
Prior art date
Application number
AT10180492T
Other languages
English (en)
Inventor
Michael Chan
Paul Leventis
David Lewis
Ketan Zaveri
Hyun Mo Yi
Chris Lane
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Application granted granted Critical
Publication of ATE542297T1 publication Critical patent/ATE542297T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17764—Structural details of configuration resources for reliability
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AT10180492T 2004-05-28 2005-05-26 Computerprogramprodukt zum programmieren einer programmierbaren logischen schaltung mit redundanz, entsprechende anordnung und verfahren ATE542297T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/856,434 US7180324B2 (en) 2004-05-28 2004-05-28 Redundancy structures and methods in a programmable logic device

Publications (1)

Publication Number Publication Date
ATE542297T1 true ATE542297T1 (de) 2012-02-15

Family

ID=35045233

Family Applications (1)

Application Number Title Priority Date Filing Date
AT10180492T ATE542297T1 (de) 2004-05-28 2005-05-26 Computerprogramprodukt zum programmieren einer programmierbaren logischen schaltung mit redundanz, entsprechende anordnung und verfahren

Country Status (4)

Country Link
US (3) US7180324B2 (de)
EP (3) EP2256930B1 (de)
JP (2) JP2006014297A (de)
AT (1) ATE542297T1 (de)

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US7589552B1 (en) 2007-10-23 2009-09-15 Altera Corporation Integrated circuit with redundancy
US20100005335A1 (en) * 2008-07-01 2010-01-07 International Business Machines Corporation Microprocessor interface with dynamic segment sparing and repair
US8234540B2 (en) 2008-07-01 2012-07-31 International Business Machines Corporation Error correcting code protected quasi-static bit communication on a high-speed bus
US7895374B2 (en) * 2008-07-01 2011-02-22 International Business Machines Corporation Dynamic segment sparing and repair in a memory system
US7772872B2 (en) * 2008-09-08 2010-08-10 Altera Corporation Multi-row block supporting row level redundancy in a PLD
US8805916B2 (en) * 2009-03-03 2014-08-12 Altera Corporation Digital signal processing circuitry with redundancy and bidirectional data paths
US8549055B2 (en) * 2009-03-03 2013-10-01 Altera Corporation Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry
US7902855B1 (en) 2010-03-03 2011-03-08 Altera Corporation Repairable IO in an integrated circuit
US8810280B2 (en) 2011-10-06 2014-08-19 Oracle International Corporation Low leakage spare gates for integrated circuits
US9236864B1 (en) 2012-01-17 2016-01-12 Altera Corporation Stacked integrated circuit with redundancy in die-to-die interconnects
US8860460B1 (en) * 2012-11-05 2014-10-14 Altera Corporation Programmable integrated circuits with redundant circuitry
WO2015015319A2 (en) 2013-05-03 2015-02-05 Blackcomb Design Automation Inc. Architecture of spare wiring structures for improved engineering change orders
US9698790B2 (en) * 2015-06-26 2017-07-04 Advanced Micro Devices, Inc. Computer architecture using rapidly reconfigurable circuits and high-bandwidth memory interfaces
KR102557310B1 (ko) * 2016-08-09 2023-07-20 에스케이하이닉스 주식회사 반도체 장치
US10241477B2 (en) * 2016-11-02 2019-03-26 Edison Labs, Inc. Adaptive control methods for buildings with redundant circuitry
US9893732B1 (en) 2016-12-22 2018-02-13 Intel Corporation Techniques for bypassing defects in rows of circuits
US10540200B2 (en) 2017-11-10 2020-01-21 Advanced Micro Devices, Inc. High performance context switching for virtualized FPGA accelerators
US10164639B1 (en) 2017-11-14 2018-12-25 Advanced Micro Devices, Inc. Virtual FPGA management and optimization system
US11368158B2 (en) 2018-06-26 2022-06-21 Intel Corporation Methods for handling integrated circuit dies with defects
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Also Published As

Publication number Publication date
JP2006014297A (ja) 2006-01-12
EP1603241A2 (de) 2005-12-07
US7180324B2 (en) 2007-02-20
JP2012029325A (ja) 2012-02-09
US7644386B1 (en) 2010-01-05
EP2256930B1 (de) 2012-01-18
US20050264318A1 (en) 2005-12-01
EP2256930A1 (de) 2010-12-01
EP1603241A3 (de) 2006-10-04
EP2146434A1 (de) 2010-01-20
US8191025B1 (en) 2012-05-29
JP5485962B2 (ja) 2014-05-07

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