ATE60689T1 - Verfahren zur spaetprogrammierung eines festwertspeichers. - Google Patents

Verfahren zur spaetprogrammierung eines festwertspeichers.

Info

Publication number: ATE60689T1
Authority: AT; Austria
Prior art keywords: transistors; rom; drain; gate; regions
Prior art date: 1985-07-29

Application number

AT86401508T

Other languages

English (en)

Inventor

Robert O Miller

Original Assignee

Sgs Thomson Microelectronics

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1985-07-29

Filing date

1986-07-07

Publication date

1991-02-15

1986-07-07 Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics

1991-02-15 Application granted granted Critical

1991-02-15 Publication of ATE60689T1 publication Critical patent/ATE60689T1/de

Links

101100020619 Arabidopsis thaliana LATE gene Proteins 0.000 title 1
239000007943 implant Substances 0.000 abstract 4
BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 abstract 3
ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract 1
229910052796 boron Inorganic materials 0.000 abstract 1

Classifications

- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/38—Doping programmed, e.g. mask ROM
- H10B20/387—Source region or drain region doping programmed
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/34—Source electrode or drain electrode programmed
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/36—Gate programmed, e.g. different gate material or no gate
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/082—Ion implantation FETs/COMs

Landscapes

Semiconductor Memories (AREA)
Read Only Memory (AREA)
Circuits Of Receivers In General (AREA)
Complex Calculations (AREA)

AT86401508T 1985-07-29 1986-07-07 Verfahren zur spaetprogrammierung eines festwertspeichers. ATE60689T1 (de)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
US06/760,206 US4649629A (en)	1985-07-29	1985-07-29	Method of late programming a read only memory
EP86401508A EP0213983B1 (de)	1985-07-29	1986-07-07	Verfahren zur Spätprogrammierung eines Festwertspeichers

Publications (1)

Publication Number	Publication Date
ATE60689T1 true ATE60689T1 (de)	1991-02-15

Family

ID=25058426

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
AT86401508T ATE60689T1 (de)	1985-07-29	1986-07-07	Verfahren zur spaetprogrammierung eines festwertspeichers.

Country Status (6)

Country	Link
US (1)	US4649629A (de)
EP (1)	EP0213983B1 (de)
JP (1)	JPH07120715B2 (de)
KR (1)	KR930008007B1 (de)
AT (1)	ATE60689T1 (de)
DE (1)	DE3677293D1 (de)

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DE3581797D1 (de) *	1984-12-27	1991-03-28	Toshiba Kawasaki Kk	Misfet mit niedrigdotiertem drain und verfahren zu seiner herstellung.
DE3618166A1 (de) *	1986-05-30	1987-12-03	Telefunken Electronic Gmbh	Lateraltransistor
JP2723147B2 (ja) *	1986-06-25	1998-03-09	株式会社日立製作所	半導体集積回路装置の製造方法
JPS63244776A (ja) *	1987-03-31	1988-10-12	Toshiba Corp	絶縁ゲ−ト型電界効果トランジスタの製造方法
IT1215558B (it) *	1987-06-11	1990-02-14	Sgs Microelettronica Spa	Procedimento di programmazione per memorie rom e tecnolgia mos con ossido di gate e giunzioni sottili.
US4923824A (en) *	1988-04-27	1990-05-08	Vtc Incorporated	Simplified method of fabricating lightly doped drain insulated gate field effect transistors
JPH0783122B2 (ja) *	1988-12-01	1995-09-06	富士電機株式会社	半導体装置の製造方法
IT1239707B (it) *	1990-03-15	1993-11-15	St Microelectrics Srl	Processo per la realizzazione di una cella di memoria rom a bassa capacita' di drain
JP2644912B2 (ja) *	1990-08-29	1997-08-25	株式会社日立製作所	真空処理装置及びその運転方法
JP2660451B2 (ja) *	1990-11-19	1997-10-08	三菱電機株式会社	半導体装置およびその製造方法
US5200802A (en) *	1991-05-24	1993-04-06	National Semiconductor Corporation	Semiconductor ROM cell programmed using source mask
US5320974A (en) *	1991-07-25	1994-06-14	Matsushita Electric Industrial Co., Ltd.	Method for making semiconductor transistor device by implanting punch through stoppers
US5894158A (en) *	1991-09-30	1999-04-13	Stmicroelectronics, Inc.	Having halo regions integrated circuit device structure
US5466957A (en) *	1991-10-31	1995-11-14	Sharp Kabushiki Kaisha	Transistor having source-to-drain nonuniformly-doped channel and method for fabricating the same
US5225357A (en) *	1992-01-02	1993-07-06	Chartered Semiconductor Manufacturing	Low P+ contact resistance formation by double implant
US5362982A (en) *	1992-04-03	1994-11-08	Matsushita Electric Industrial Co., Ltd.	Insulated gate FET with a particular LDD structure
JP3202784B2 (ja) *	1992-04-13	2001-08-27	三菱電機株式会社	マスクｒｏｍ半導体装置およびその製造方法
US5432103A (en) *	1992-06-22	1995-07-11	National Semiconductor Corporation	Method of making semiconductor ROM cell programmed using source mask
EP0575688B1 (de) *	1992-06-26	1998-05-27	STMicroelectronics S.r.l.	Programmierung von LDD-ROM-Zellen
KR0140691B1 (ko) *	1992-08-20	1998-06-01	문정환	반도체 장치의 마스크롬 제조방법
US5559044A (en) *	1992-09-21	1996-09-24	Siliconix Incorporated	BiCDMOS process technology
JP3050717B2 (ja) *	1993-03-24	2000-06-12	シャープ株式会社	半導体装置の製造方法
US5500379A (en) *	1993-06-25	1996-03-19	Matsushita Electric Industrial Co., Ltd.	Method of manufacturing semiconductor device
US5736420A (en) *	1993-08-20	1998-04-07	National Semiconductor Corporation	Process for fabricating read only memories, with programming step performed midway through the fabrication process
US5374565A (en) *	1993-10-22	1994-12-20	United Microelectronics Corporation	Method for ESD protection improvement
EP0657929B1 (de) *	1993-12-07	2004-08-18	Infineon Technologies AG	Verfahren zur Herstellung von MOSFETS mit verbesserten Kurz-Kanal Effekten
JP3367776B2 (ja) *	1993-12-27	2003-01-20	株式会社東芝	半導体装置
US5389565A (en) *	1994-01-07	1995-02-14	Zilog, Inc.	Method of fabricating high threshold metal oxide silicon read-only-memory transistors
GB2291255A (en) *	1994-07-12	1996-01-17	Mosel Vitelic Inc	ROM coding by implant
JPH08125180A (ja) *	1994-10-25	1996-05-17	Mitsubishi Electric Corp	半導体装置およびその製造方法
US5532175A (en) *	1995-04-17	1996-07-02	Motorola, Inc.	Method of adjusting a threshold voltage for a semiconductor device fabricated on a semiconductor on insulator substrate
US5629546A (en)	1995-06-21	1997-05-13	Micron Technology, Inc.	Static memory cell and method of manufacturing a static memory cell
FR2738089B1 (fr) *	1995-08-24	1997-10-31	Sgs Thomson Microelectronics	Dispositif de correction de linearite de rampes d'un signal en dents de scie et generateur d'un tel signal
FR2737597B1 (fr)	1995-07-31	1997-08-29	Sgs Thomson Microelectronics	Procede de programmation d'une cellule de memoire morte et memoire associee
US5917219A (en) *	1995-10-09	1999-06-29	Texas Instruments Incorporated	Semiconductor devices with pocket implant and counter doping
US5719081A (en) *	1995-11-03	1998-02-17	Motorola, Inc.	Fabrication method for a semiconductor device on a semiconductor on insulator substrate using a two stage threshold adjust implant
JP2787908B2 (ja) *	1995-12-25	1998-08-20	日本電気株式会社	半導体装置の製造方法
KR100213201B1 (ko) *	1996-05-15	1999-08-02	윤종용	씨모스 트랜지스터 및 그 제조방법
TW425692B (en) *	1996-12-13	2001-03-11	Hitachi Ltd	Semiconductor integrated circuit apparatus and its fabrication method
US6037227A (en) *	1997-06-03	2000-03-14	United Microelectronics Corp.	Method of making high density mask ROM having a two level bit line
KR100237900B1 (ko) *	1997-07-22	2000-01-15	김영환	반도체 기억 소자
US6025232A (en)	1997-11-12	2000-02-15	Micron Technology, Inc.	Methods of forming field effect transistors and related field effect transistor constructions
EP0957521A1 (de)	1998-05-11	1999-11-17	STMicroelectronics S.r.l.	Speicherzellenanordnung hergestellt durch ein Self-Aligned-Source-Verfahren (SAS), die Festwertspeicherzellen (ROM) aufweist, und deren Herstellungsverfahren
DE19929675A1 (de) *	1999-06-28	2001-04-12	Infineon Technologies Ag	Verfahren zur Herstellung von ROM-Speicherzellen
US6077746A (en) *	1999-08-26	2000-06-20	Taiwan Semiconductor Manufacturing Company	Using p-type halo implant as ROM cell isolation in flat-cell mask ROM process
US6432777B1 (en)	2001-06-06	2002-08-13	International Business Machines Corporation	Method for increasing the effective well doping in a MOSFET as the gate length decreases
CN1225782C (zh) *	2002-12-27	2005-11-02	中芯国际集成电路制造(上海)有限公司	一种掩膜式只读存储器工艺与元件
US6913980B2 (en) *	2003-06-30	2005-07-05	Texas Instruments Incorporated	Process method of source drain spacer engineering to improve transistor capacitance
US7709896B2 (en) *	2006-03-08	2010-05-04	Infineon Technologies Ag	ESD protection device and method
KR100890613B1 (ko) *	2007-01-26	2009-03-27	삼성전자주식회사	마스크롬 소자 및 그 제조 방법
KR100868097B1 (ko) *	2007-06-12	2008-11-11	삼성전자주식회사	마스크롬 소자, 그것을 포함하는 반도체 소자 및 그들의제조 방법

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US4472871A (en) *	1978-09-21	1984-09-25	Mostek Corporation	Method of making a plurality of MOSFETs having different threshold voltages
JPS5570072A (en) *	1978-11-21	1980-05-27	Chiyou Lsi Gijutsu Kenkyu Kumiai	Semiconductor read only memory
US4376947A (en) *	1979-09-04	1983-03-15	Texas Instruments Incorporated	Electrically programmable floating gate semiconductor memory device
US4406049A (en) *	1980-12-11	1983-09-27	Rockwell International Corporation	Very high density cells comprising a ROM and method of manufacturing same
DE3279662D1 (en) *	1981-12-30	1989-06-01	Thomson Components Mostek Corp	Triple diffused short channel device structure
US4419809A (en) *	1981-12-30	1983-12-13	International Business Machines Corporation	Fabrication process of sub-micrometer channel length MOSFETs
US4455742A (en) *	1982-06-07	1984-06-26	Westinghouse Electric Corp.	Method of making self-aligned memory MNOS-transistor
NL8202686A (nl) *	1982-07-05	1984-02-01	Philips Nv	Werkwijze ter vervaardiging van een veldeffektinrichting met geisoleerde stuurelektrode, en inrichting vervaardigd volgens de werkwijze.
JPS59100562A (ja) *	1982-11-30	1984-06-09	Mitsubishi Electric Corp	読み出し専用半導体記憶装置の製造方法
US4536944A (en) *	1982-12-29	1985-08-27	International Business Machines Corporation	Method of making ROM/PLA semiconductor device by late stage personalization
JPS59138379A (ja) *	1983-01-27	1984-08-08	Toshiba Corp	半導体装置の製造方法
US4513494A (en) *	1983-07-19	1985-04-30	American Microsystems, Incorporated	Late mask process for programming read only memories
US4590665A (en) *	1984-12-10	1986-05-27	Solid State Scientific, Inc.	Method for double doping sources and drains in an EPROM

1985
- 1985-07-29 US US06/760,206 patent/US4649629A/en not_active Expired - Lifetime
1986
- 1986-07-07 EP EP86401508A patent/EP0213983B1/de not_active Expired - Lifetime
- 1986-07-07 AT AT86401508T patent/ATE60689T1/de active
- 1986-07-07 DE DE8686401508T patent/DE3677293D1/de not_active Expired - Lifetime
- 1986-07-29 JP JP17859186A patent/JPH07120715B2/ja not_active Expired - Fee Related
- 1986-07-29 KR KR1019860006213A patent/KR930008007B1/ko not_active Expired - Fee Related

Also Published As

Publication number	Publication date
KR930008007B1 (ko)	1993-08-25
KR870001665A (ko)	1987-03-17
EP0213983B1 (de)	1991-01-30
EP0213983A3 (en)	1987-07-01
JPS6285462A (ja)	1987-04-18
DE3677293D1 (de)	1991-03-07
EP0213983A2 (de)	1987-03-11
JPH07120715B2 (ja)	1995-12-20
US4649629A (en)	1987-03-17

Publication	Publication Date	Title
ATE60689T1 (de)	1991-02-15	Verfahren zur spaetprogrammierung eines festwertspeichers.
DE3581642D1 (de)	1991-03-07	Antimikrobielle antistatische siloxanzusammensetzungen und verfahren zur behandlung von materialien.
DE3581797D1 (de)	1991-03-28	Misfet mit niedrigdotiertem drain und verfahren zu seiner herstellung.
KR880701964A (ko)	1988-11-07	전계효과 트랜지스터용 t- 게이트 전극 및 이의 제조방법
DE3576883D1 (de)	1990-05-03	Silizium-auf-isolator-transistor.
FI854349A7 (fi)	1986-05-09	Biohapetusprosessien stimulointi maanalaisissa kohteissa.
DE3585464D1 (de)	1992-04-09	Intelligente karte.
ATE36094T1 (de)	1988-08-15	Verfahren zum gleichzeitigen herstellen von schnellen kurzkanal- und spannungsfesten mostransistoren in vlsi-schaltungen.
DE3580409D1 (de)	1990-12-13	Chip-karte und chip-kartenleser.
DE3586423D1 (de)	1992-09-03	Hitzehaertbare siliconharze, deren verwendung und stabilisator dafuer.
DE3881304D1 (de)	1993-07-01	Mos-transistor.
DE3584013D1 (de)	1991-10-10	Zubereitung zur behandlung von psoriasis.
DE3579419D1 (de)	1990-10-04	Einstufiges hydrobehandlungsverfahren.
DE3382387D1 (de)	1991-10-02	Loesungen von aminosaeuren zur parenteralen naehrung sowie dosierverfahren und verwendung.
DE3578271D1 (de)	1990-07-19	Feldeffekttransistor mit einem schottky-gate und herstellungsverfahren dafuer.
FI871768A0 (fi)	1987-04-22	Mjukgoerande detergentkompositioner innehaollande amidmjukgoeringsmedel.
DE3576612D1 (de)	1990-04-19	Halbleiteranordnung mit mos-transistoren.
DE3578533D1 (de)	1990-08-09	Halbleiterbauelement mit von source- und/oder drain-gebieten umgebenen anschlussflaechen.
DE3579675D1 (de)	1990-10-18	Kombinierter lateraler mos/bipolarer transistor hoher leitfaehigkeit.
FI854976A7 (fi)	1986-06-18	Tekoturpeen käsittelymenetelmä.
DE3788438D1 (de)	1994-01-27	Methode zur Herstellung von integrierten elektronischen Vorrichtungen, insbesondere Hochspannungs-P-Kanal-MOS-Transistoren.
IT8720872A0 (it)	1987-06-11	Procedimento di programmazione per memorie rom e tecnolgia mos con ossido di gate e giunzioni sottili.
DE3586148D1 (de)	1992-07-09	Flaechenbehandlungsverfahren.
DE3583064D1 (de)	1991-07-11	Supraleitender transistor.
DE3860165D1 (de)	1990-06-28	Nitrifikationshemmendes mittel.