ATE74228T1 - Verfahren zur herstellung von halbleiterschaltungen um einen bipolaren transistor mit extrinsischen basengebieten zu bilden. - Google Patents

Verfahren zur herstellung von halbleiterschaltungen um einen bipolaren transistor mit extrinsischen basengebieten zu bilden.

Info

Publication number
ATE74228T1
ATE74228T1 AT86308296T AT86308296T ATE74228T1 AT E74228 T1 ATE74228 T1 AT E74228T1 AT 86308296 T AT86308296 T AT 86308296T AT 86308296 T AT86308296 T AT 86308296T AT E74228 T1 ATE74228 T1 AT E74228T1
Authority
AT
Austria
Prior art keywords
bipolar transistor
base regions
extrinsic base
semiconductor circuits
making semiconductor
Prior art date
Application number
AT86308296T
Other languages
English (en)
Inventor
Shiao-Hoo Chang
Matthew Weinberg
Mammen Thomas
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE74228T1 publication Critical patent/ATE74228T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H10P30/212—Through-implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/01—Bipolar transistors-ion implantation

Landscapes

  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
AT86308296T 1985-11-01 1986-10-24 Verfahren zur herstellung von halbleiterschaltungen um einen bipolaren transistor mit extrinsischen basengebieten zu bilden. ATE74228T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/794,357 US4669179A (en) 1985-11-01 1985-11-01 Integrated circuit fabrication process for forming a bipolar transistor having extrinsic base regions
EP86308296A EP0221742B1 (de) 1985-11-01 1986-10-24 Verfahren zur Herstellung von Halbleiterschaltungen um einen bipolaren Transistor mit extrinsischen Basengebieten zu bilden

Publications (1)

Publication Number Publication Date
ATE74228T1 true ATE74228T1 (de) 1992-04-15

Family

ID=25162417

Family Applications (1)

Application Number Title Priority Date Filing Date
AT86308296T ATE74228T1 (de) 1985-11-01 1986-10-24 Verfahren zur herstellung von halbleiterschaltungen um einen bipolaren transistor mit extrinsischen basengebieten zu bilden.

Country Status (6)

Country Link
US (1) US4669179A (de)
EP (1) EP0221742B1 (de)
JP (1) JPS62113471A (de)
AT (1) ATE74228T1 (de)
DE (1) DE3684555D1 (de)
ES (1) ES2030389T3 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4812417A (en) * 1986-07-30 1989-03-14 Mitsubishi Denki Kabushiki Kaisha Method of making self aligned external and active base regions in I.C. processing
US4740478A (en) * 1987-01-30 1988-04-26 Motorola Inc. Integrated circuit method using double implant doping
US5258317A (en) * 1992-02-13 1993-11-02 Integrated Device Technology, Inc. Method for using a field implant mask to correct low doping levels at the outside edges of the base in a walled-emitter transistor structure
US5338695A (en) * 1992-11-24 1994-08-16 National Semiconductor Corporation Making walled emitter bipolar transistor with reduced base narrowing
US5369052A (en) * 1993-12-06 1994-11-29 Motorola, Inc. Method of forming dual field oxide isolation
US5548158A (en) * 1994-09-02 1996-08-20 National Semiconductor Corporation Structure of bipolar transistors with improved output current-voltage characteristics
US5617357A (en) * 1995-04-07 1997-04-01 Advanced Micro Devices, Inc. Flash EEPROM memory with improved discharge speed using substrate bias and method therefor
US5849613A (en) * 1997-10-23 1998-12-15 Chartered Semiconductor Manufacturing Ltd. Method and mask structure for self-aligning ion implanting to form various device structures
SE518710C2 (sv) * 2000-06-26 2002-11-12 Ericsson Telefon Ab L M Förfarande för att förbättra transistorprestanda samt transistoranordning och integrerad krets

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2358748A1 (fr) * 1976-07-15 1978-02-10 Radiotechnique Compelec Procede d'autoalignement des elements d'un dispositif semi-conducteur et dispositif realise suivant ce procede
US4111726A (en) * 1977-04-01 1978-09-05 Burroughs Corporation Bipolar integrated circuit process by separately forming active and inactive base regions
US4118250A (en) * 1977-12-30 1978-10-03 International Business Machines Corporation Process for producing integrated circuit devices by ion implantation
US4484211A (en) * 1981-02-04 1984-11-20 Matsushita Electric Industrial Co., Ltd. Oxide walled emitter
DE3115029A1 (de) * 1981-04-14 1982-11-04 Deutsche Itt Industries Gmbh, 7800 Freiburg "verfahren zur herstellung eines integrierten bipolaren planartransistors"
FR2508704B1 (fr) * 1981-06-26 1985-06-07 Thomson Csf Procede de fabrication de transistors bipolaires integres de tres petites dimensions
US4433471A (en) * 1982-01-18 1984-02-28 Fairchild Camera & Instrument Corporation Method for the formation of high density memory cells using ion implantation techniques
US4498227A (en) * 1983-07-05 1985-02-12 Fairchild Camera & Instrument Corporation Wafer fabrication by implanting through protective layer
US4573256A (en) * 1983-08-26 1986-03-04 International Business Machines Corporation Method for making a high performance transistor integrated circuit
US4574469A (en) * 1984-09-14 1986-03-11 Motorola, Inc. Process for self-aligned buried layer, channel-stop, and isolation

Also Published As

Publication number Publication date
JPS62113471A (ja) 1987-05-25
US4669179A (en) 1987-06-02
EP0221742A2 (de) 1987-05-13
EP0221742B1 (de) 1992-03-25
ES2030389T3 (es) 1992-11-01
EP0221742A3 (en) 1989-07-05
DE3684555D1 (de) 1992-04-30

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee