BE894797A - Procede de definition d'elements de taille inferieure au micron dans des dispositifs semiconducteurs - Google Patents

Procede de definition d'elements de taille inferieure au micron dans des dispositifs semiconducteurs

Info

Publication number
BE894797A
BE894797A BE0/209320A BE209320A BE894797A BE 894797 A BE894797 A BE 894797A BE 0/209320 A BE0/209320 A BE 0/209320A BE 209320 A BE209320 A BE 209320A BE 894797 A BE894797 A BE 894797A
Authority
BE
Belgium
Prior art keywords
semiconductor devices
micron size
elements under
defining elements
under micron
Prior art date
Application number
BE0/209320A
Other languages
English (en)
Inventor
R M Levin
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co filed Critical Western Electric Co
Publication of BE894797A publication Critical patent/BE894797A/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/944—Shadow
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing
BE0/209320A 1981-10-28 1982-10-25 Procede de definition d'elements de taille inferieure au micron dans des dispositifs semiconducteurs BE894797A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/315,757 US4441931A (en) 1981-10-28 1981-10-28 Method of making self-aligned guard regions for semiconductor device elements

Publications (1)

Publication Number Publication Date
BE894797A true BE894797A (fr) 1983-02-14

Family

ID=23225928

Family Applications (1)

Application Number Title Priority Date Filing Date
BE0/209320A BE894797A (fr) 1981-10-28 1982-10-25 Procede de definition d'elements de taille inferieure au micron dans des dispositifs semiconducteurs

Country Status (9)

Country Link
US (1) US4441931A (fr)
JP (1) JPS5884432A (fr)
BE (1) BE894797A (fr)
CA (1) CA1186809A (fr)
DE (1) DE3239819A1 (fr)
FR (1) FR2515425B1 (fr)
GB (1) GB2108759B (fr)
IT (1) IT1153577B (fr)
NL (1) NL8204152A (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5950567A (ja) * 1982-09-16 1984-03-23 Hitachi Ltd 電界効果トランジスタの製造方法
JPS60201666A (ja) * 1984-03-27 1985-10-12 Nec Corp 半導体装置
DE3576766D1 (de) * 1984-10-26 1990-04-26 Siemens Ag Schottky-kontakt auf einer halbleiteroberflaeche und verfahren zu dessen herstellung.
US4655875A (en) * 1985-03-04 1987-04-07 Hitachi, Ltd. Ion implantation process
US4712291A (en) * 1985-06-06 1987-12-15 The United States Of America As Represented By The Secretary Of The Air Force Process of fabricating TiW/Si self-aligned gate for GaAs MESFETs
US4669178A (en) * 1986-05-23 1987-06-02 International Business Machines Corporation Process for forming a self-aligned low resistance path in semiconductor devices
US5141891A (en) * 1988-11-09 1992-08-25 Mitsubishi Denki Kabushiki Kaisha MIS-type semiconductor device of LDD structure and manufacturing method thereof
US5120668A (en) * 1991-07-10 1992-06-09 Ibm Corporation Method of forming an inverse T-gate FET transistor
US6040222A (en) * 1999-02-02 2000-03-21 United Microelectronics Corp. Method for fabricating an electrostatistic discharge protection device to protect an integrated circuit
US6514840B2 (en) * 1999-04-13 2003-02-04 International Business Machines Corporation Micro heating of selective regions
US6699775B2 (en) * 2000-02-22 2004-03-02 International Rectifier Corporation Manufacturing process for fast recovery diode
US20060022291A1 (en) * 2004-07-28 2006-02-02 Vladimir Drobny Unguarded schottky diodes with sidewall spacer at the perimeter of the diode
US8901699B2 (en) 2005-05-11 2014-12-02 Cree, Inc. Silicon carbide junction barrier Schottky diodes with suppressed minority carrier injection
JP2011129619A (ja) * 2009-12-16 2011-06-30 Toyota Motor Corp 半導体装置の製造方法
KR101534121B1 (ko) 2011-01-07 2015-07-09 유니버시티 오브 캘커타 삼차원 물체의 보호 구역을 계산하도록 구성되는 방법 및 시스템

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3920861A (en) * 1972-12-18 1975-11-18 Rca Corp Method of making a semiconductor device
DE2432719B2 (de) * 1974-07-08 1977-06-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zum erzeugen von feinen strukturen aus aufdampfbaren materialien auf einer unterlage und anwendung des verfahrens
US4037307A (en) * 1975-03-21 1977-07-26 Bell Telephone Laboratories, Incorporated Methods for making transistor structures
US4026740A (en) * 1975-10-29 1977-05-31 Intel Corporation Process for fabricating narrow polycrystalline silicon members
JPS5263680A (en) * 1975-11-19 1977-05-26 Matsushita Electric Ind Co Ltd Production of semiconductor device
JPS5819129B2 (ja) * 1975-12-10 1983-04-16 株式会社東芝 ハンドウタイソウチノ セイゾウホウホウ
JPS52147063A (en) * 1976-06-02 1977-12-07 Toshiba Corp Semiconductor electrode forming method
DE2641334C2 (de) * 1976-09-14 1985-06-27 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Herstellung integrierter MIS-Schaltungen
US4145459A (en) * 1978-02-02 1979-03-20 Rca Corporation Method of making a short gate field effect transistor
DE2842589A1 (de) * 1978-09-29 1980-05-08 Siemens Ag Feldeffekttransistor mit verringerter substratsteuerung der kanalbreite
US4261095A (en) * 1978-12-11 1981-04-14 International Business Machines Corporation Self aligned schottky guard ring
JPS56125843A (en) * 1980-03-07 1981-10-02 Chiyou Lsi Gijutsu Kenkyu Kumiai Forming method of fine pattern
JPS56131933A (en) * 1980-03-19 1981-10-15 Chiyou Lsi Gijutsu Kenkyu Kumiai Forming method of pattern of metallic film

Also Published As

Publication number Publication date
JPS5884432A (ja) 1983-05-20
IT8223909A0 (it) 1982-10-25
IT8223909A1 (it) 1984-04-25
NL8204152A (nl) 1983-05-16
FR2515425B1 (fr) 1986-01-17
GB2108759A (en) 1983-05-18
IT1153577B (it) 1987-01-14
FR2515425A1 (fr) 1983-04-29
GB2108759B (en) 1985-07-17
CA1186809A (fr) 1985-05-07
DE3239819A1 (de) 1983-05-05
US4441931A (en) 1984-04-10

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Legal Events

Date Code Title Description
RE Patent lapsed

Owner name: WESTERN ELECTRIC CY INC.

Effective date: 19901031