BE895382A - Systeme de synchronisation de rythme - Google Patents

Systeme de synchronisation de rythme

Info

Publication number
BE895382A
BE895382A BE2/59957A BE2059957A BE895382A BE 895382 A BE895382 A BE 895382A BE 2/59957 A BE2/59957 A BE 2/59957A BE 2059957 A BE2059957 A BE 2059957A BE 895382 A BE895382 A BE 895382A
Authority
BE
Belgium
Prior art keywords
synchronization system
rhythm synchronization
rhythm
synchronization
Prior art date
Application number
BE2/59957A
Other languages
English (en)
Inventor
A R Khan
I L Edwards
Original Assignee
Gte Automatic Electric Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gte Automatic Electric Inc filed Critical Gte Automatic Electric Inc
Publication of BE895382A publication Critical patent/BE895382A/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
BE2/59957A 1981-12-18 1982-12-17 Systeme de synchronisation de rythme BE895382A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/332,137 US4412342A (en) 1981-12-18 1981-12-18 Clock synchronization system

Publications (1)

Publication Number Publication Date
BE895382A true BE895382A (fr) 1983-04-15

Family

ID=23296864

Family Applications (1)

Application Number Title Priority Date Filing Date
BE2/59957A BE895382A (fr) 1981-12-18 1982-12-17 Systeme de synchronisation de rythme

Country Status (5)

Country Link
US (1) US4412342A (fr)
JP (1) JPS58111440A (fr)
BE (1) BE895382A (fr)
CA (1) CA1176714A (fr)
IT (1) IT1191141B (fr)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4521897A (en) * 1983-07-29 1985-06-04 Zenith Electronics Corporation Apparatus for synchronizing the operation of master and slave counters
US4635249A (en) * 1985-05-03 1987-01-06 At&T Information Systems Inc. Glitchless clock signal control circuit for a duplicated system
US4758747A (en) * 1986-05-30 1988-07-19 Advanced Micro Devices, Inc. Programmable logic device with buried registers selectively multiplexed with output registers to ports, and preload circuitry therefor
US4733353A (en) * 1985-12-13 1988-03-22 General Electric Company Frame synchronization of multiply redundant computers
US4651103A (en) 1985-12-30 1987-03-17 At&T Company Phase adjustment system
US4714924A (en) * 1985-12-30 1987-12-22 Eta Systems, Inc. Electronic clock tuning system
US4860006A (en) * 1986-06-05 1989-08-22 Michael Barall Heartbeat collision avoidance method and circuit
US4769558A (en) * 1986-07-09 1988-09-06 Eta Systems, Inc. Integrated circuit clock bus layout delay system
JPS6345670A (ja) * 1986-08-13 1988-02-26 Hitachi Ltd プロセツサ間同期装置
US4868514A (en) * 1987-11-17 1989-09-19 International Business Machines Corporation Apparatus and method for digital compensation of oscillator drift
US4899351A (en) * 1988-07-18 1990-02-06 Western Digital Corporation Transient free clock switch logic
US4977581A (en) * 1988-08-18 1990-12-11 Unisys Corporation Multiple frequency clock system
DE3833940A1 (de) * 1988-09-22 1990-04-05 Siemens Ag Verfahren zur neusynchronisation einer vermittlungsstelle in einem fernmeldenetz
JPH0797328B2 (ja) * 1988-10-25 1995-10-18 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン フオールト・トレラント同期システム
US5118975A (en) * 1990-03-05 1992-06-02 Thinking Machines Corporation Digital clock buffer circuit providing controllable delay
CA2047641C (fr) * 1991-07-23 2000-01-11 Ed Gancarcik Interface a tarif de base
US5812832A (en) * 1993-01-29 1998-09-22 Advanced Micro Devices, Inc. Digital clock waveform generator and method for generating a clock signal
US5422914A (en) * 1993-09-07 1995-06-06 Motorola, Inc. System and method for synchronizing data communications between two devices operating at different clock frequencies
US5533072A (en) * 1993-11-12 1996-07-02 International Business Machines Corporation Digital phase alignment and integrated multichannel transceiver employing same
US5574753A (en) * 1993-12-23 1996-11-12 Unisys Corporation Glitch free clock start/stop control circuit for outputting a single clock signal and a single sync signal from a plurality of sync signal inputs and a plurality of clock signal inputs
US5422915A (en) * 1993-12-23 1995-06-06 Unisys Corporation Fault tolerant clock distribution system
US6064707A (en) 1995-12-22 2000-05-16 Zilog, Inc. Apparatus and method for data synchronizing and tracking
US6738442B1 (en) 2000-01-19 2004-05-18 Agere Systems Inc. Pulse detection and synchronization system
CN1612959A (zh) * 2002-01-04 2005-05-04 纳幕尔杜邦公司 具有拉伸能力改进的密封外表面的粘合聚酯填充纤维棉絮
US6970045B1 (en) 2003-06-25 2005-11-29 Nel Frequency Controls, Inc. Redundant clock module
DE102004027503B4 (de) * 2004-06-04 2012-08-16 Robert Bosch Gmbh Verfahren zur Etablierung einer globalen Zeitbasis in einem zeitgesteuerten Kommunikationssystem und Kommunikationssystem
EP2138815B1 (fr) * 2008-06-25 2013-11-20 Semiconductor Energy Laboratory Co, Ltd. Dispositif photométrique

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4019143A (en) * 1976-05-10 1977-04-19 Bell Telephone Laboratories, Incorporated Standby apparatus for clock signal generators
US4156200A (en) * 1978-03-20 1979-05-22 Bell Telephone Laboratories, Incorporated High reliability active-standby clock arrangement
US4282493A (en) * 1979-07-02 1981-08-04 Motorola, Inc. Redundant clock signal generating circuitry

Also Published As

Publication number Publication date
IT1191141B (it) 1988-02-24
JPS58111440A (ja) 1983-07-02
CA1176714A (fr) 1984-10-23
IT8224813A0 (it) 1982-12-17
IT8224813A1 (it) 1984-06-17
US4412342A (en) 1983-10-25

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Legal Events

Date Code Title Description
RE Patent lapsed

Owner name: GTE AUTOMATIC ELECTRIC INC.

Effective date: 19891231