BR9909652A - Dispositivo de circuito para a redução da corrente de fuga - Google Patents

Dispositivo de circuito para a redução da corrente de fuga

Info

Publication number
BR9909652A
BR9909652A BR9909652-8A BR9909652A BR9909652A BR 9909652 A BR9909652 A BR 9909652A BR 9909652 A BR9909652 A BR 9909652A BR 9909652 A BR9909652 A BR 9909652A
Authority
BR
Brazil
Prior art keywords
leakage current
reducing leakage
circuit device
circuit
voltage
Prior art date
Application number
BR9909652-8A
Other languages
English (en)
Inventor
Joerg Berthold
Mathias Eberlein
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of BR9909652A publication Critical patent/BR9909652A/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Control Of Electrical Variables (AREA)
  • Electronic Switches (AREA)

Abstract

Patente de Invenção: <B>"DISPOSIçãO DE CIRCUITO PARA A REDUçãO DA CORRENTE DE FUGA"<D>. A invenção refere-se a uma disposição de circuito com partes de circuito (2, 3) constituídas por transistores com baixa tensão de corte (transistores-NV). Para a redução da corrente de fuga das partes de circuito (2, 3) a parte de circuito é acoplada, pela interligação de um transistor de comutação (MP1, MN1) de alta tensão de corte (transistor-HV), com uma tensão de suprimento (VDD, VSS) e em paralelo com o transistor de comutação-HV (MP1, MN1) é ligado um transistor de comando-NV (MNH1, MPH1).
BR9909652-8A 1998-03-16 1999-03-11 Dispositivo de circuito para a redução da corrente de fuga BR9909652A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19811353A DE19811353C1 (de) 1998-03-16 1998-03-16 Schaltungsanordnung zur Reduzierung des Leckstromes
PCT/DE1999/000677 WO1999048208A1 (de) 1998-03-16 1999-03-11 Schaltungsanordnung zur reduzierung des leckstromes

Publications (1)

Publication Number Publication Date
BR9909652A true BR9909652A (pt) 2000-11-21

Family

ID=7861059

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9909652-8A BR9909652A (pt) 1998-03-16 1999-03-11 Dispositivo de circuito para a redução da corrente de fuga

Country Status (8)

Country Link
EP (1) EP1064726A1 (pt)
JP (1) JP2002507852A (pt)
KR (1) KR20010041927A (pt)
CN (1) CN1301430A (pt)
BR (1) BR9909652A (pt)
DE (1) DE19811353C1 (pt)
RU (1) RU2000125907A (pt)
WO (1) WO1999048208A1 (pt)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6166985A (en) * 1999-04-30 2000-12-26 Intel Corporation Integrated circuit low leakage power circuitry for use with an advanced CMOS process
JP3727838B2 (ja) * 2000-09-27 2005-12-21 株式会社東芝 半導体集積回路
DE10128732C1 (de) * 2001-06-13 2002-05-29 Infineon Technologies Ag Verfahren und Vorrichtung zur Abschätzung der Stromaufnahme von Schaltungsteilen
US6515935B1 (en) * 2001-10-19 2003-02-04 Hewlett-Packard Company Method and apparatus for reducing average power in memory arrays by switching a diode in or out of the ground path
FR2838256A1 (fr) * 2002-04-08 2003-10-10 St Microelectronics Sa Procede de mise en veille d'un composant et circuit integre associe
US6611451B1 (en) * 2002-06-28 2003-08-26 Texas Instruments Incorporated Memory array and wordline driver supply voltage differential in standby
WO2004075406A1 (en) * 2003-02-19 2004-09-02 Koninklijke Philips Electronics, N.V. Leakage power control
US7227383B2 (en) 2004-02-19 2007-06-05 Mosaid Delaware, Inc. Low leakage and data retention circuitry
CA2595375A1 (en) * 2004-02-19 2005-09-09 Mosaid Technologies Corporation Low leakage and data retention circuitry
WO2009144661A1 (en) * 2008-05-27 2009-12-03 Nxp B.V. Integrated circuit and integrated circuit control method
DE102008053533A1 (de) * 2008-10-28 2010-04-29 Atmel Automotive Gmbh Schaltung, Verfahren zur Steuerung und Verwendung einer Schaltung für einen Ruhemodus und einen Betriebsmodus
DE102014107545A1 (de) 2014-05-28 2015-12-03 Phoenix Contact Gmbh & Co. Kg Energieversorgungsgerät
US11599185B2 (en) * 2015-07-22 2023-03-07 Synopsys, Inc. Internet of things (IoT) power and performance management technique and circuit methodology

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100254134B1 (ko) * 1991-11-08 2000-04-15 나시모토 류우조오 대기시 전류저감회로를 가진 반도체 집적회로
US5614847A (en) * 1992-04-14 1997-03-25 Hitachi, Ltd. Semiconductor integrated circuit device having power reduction mechanism
US5596286A (en) * 1993-11-12 1997-01-21 Texas Instruments Incorporated Current limiting devices to reduce leakage, photo, or stand-by current in an integrated circuit
JP3725911B2 (ja) * 1994-06-02 2005-12-14 株式会社ルネサステクノロジ 半導体装置
JP3561012B2 (ja) * 1994-11-07 2004-09-02 株式会社ルネサステクノロジ 半導体集積回路装置
DE19515417C2 (de) * 1995-04-26 1998-10-15 Siemens Ag Schaltungsanordnung zum Ansteuern eines Leistungs-MOSFET
EP0928068A1 (en) * 1997-12-31 1999-07-07 STMicroelectronics S.r.l. Low consumption TTL-CMOS input buffer stage

Also Published As

Publication number Publication date
EP1064726A1 (de) 2001-01-03
CN1301430A (zh) 2001-06-27
RU2000125907A (ru) 2002-09-10
KR20010041927A (ko) 2001-05-25
DE19811353C1 (de) 1999-07-22
WO1999048208A1 (de) 1999-09-23
JP2002507852A (ja) 2002-03-12

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Legal Events

Date Code Title Description
B08F Application fees: application dismissed [chapter 8.6 patent gazette]

Free format text: REFERENTE A 4O,5O6O, 7O E 8O ANUIDADES

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 1911 DE 21/08/2007.