BRPI0611883A8 - microcomputador e método para testar o mesmo - Google Patents

microcomputador e método para testar o mesmo

Info

Publication number
BRPI0611883A8
BRPI0611883A8 BRPI0611883A BRPI0611883A BRPI0611883A8 BR PI0611883 A8 BRPI0611883 A8 BR PI0611883A8 BR PI0611883 A BRPI0611883 A BR PI0611883A BR PI0611883 A BRPI0611883 A BR PI0611883A BR PI0611883 A8 BRPI0611883 A8 BR PI0611883A8
Authority
BR
Brazil
Prior art keywords
flip
flop
data
clock
synchronous
Prior art date
Application number
BRPI0611883A
Other languages
English (en)
Inventor
Namura Ken
Sugimoto Mitsuru
Yokota Toshihiko
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BRPI0611883A2 publication Critical patent/BRPI0611883A2/pt
Publication of BRPI0611883A8 publication Critical patent/BRPI0611883A8/pt
Publication of BRPI0611883B1 publication Critical patent/BRPI0611883B1/pt

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2812—Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2815—Functional tests, e.g. boundary scans, using the normal I/O contacts
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/31855—Interconnection testing, e.g. crosstalk, shortcircuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Microcomputers (AREA)

Abstract

microcomputador e método para testar o mesmo. problema: para alcançar um teste em velocidade de uma interface sincrona de fonte dentro de asic em nível de placa. solução: um microcomputador (asic) incorpora uma pluralidade de ic conectados por uso de interfaces síncronas de fonte. em um ic no lado da transmissão de dados, para começar, um flip-flop de saída de dados (fi) e um fli-flop de saída de sincronismo de relógio (f2) inserem dados de teste. então um circuito pll (11) para gerar uma operação de relógio em um modo de operação real gera um sinal de relógio. de acordo com este sinal de relógio, um primeiro e um segundo flip-flop liberam os dados de teste e o relógio de sincronismo. por outro lado, em um ic, no lado de recepção dos dados, os flip-flops de recepção de dados f3, f4) tomam nos dados de teste liberados do flip-flop (fl) de acordo com os dados de relógio de sincronismo liberados do flip-flop (f2).
BRPI0611883-6A 2005-06-10 2006-06-08 Microcomputador e método para testar o mesmo BRPI0611883B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2005171268 2005-06-10
JP2005-171268 2005-06-10
PCT/JP2006/311551 WO2006132329A1 (ja) 2005-06-10 2006-06-08 マイクロコンピュータ及びそのテスト方法

Publications (3)

Publication Number Publication Date
BRPI0611883A2 BRPI0611883A2 (pt) 2010-10-05
BRPI0611883A8 true BRPI0611883A8 (pt) 2019-01-08
BRPI0611883B1 BRPI0611883B1 (pt) 2019-07-30

Family

ID=37498525

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0611883-6A BRPI0611883B1 (pt) 2005-06-10 2006-06-08 Microcomputador e método para testar o mesmo

Country Status (9)

Country Link
US (1) US7793183B2 (pt)
EP (1) EP1890234B1 (pt)
JP (1) JP4701244B2 (pt)
CN (1) CN100504802C (pt)
AT (1) ATE448517T1 (pt)
BR (1) BRPI0611883B1 (pt)
DE (1) DE602006010372D1 (pt)
RU (1) RU2374679C2 (pt)
WO (1) WO2006132329A1 (pt)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2374679C2 (ru) 2005-06-10 2009-11-27 Интернэшнл Бизнес Машинз Корпорейшн Микрокомпьютер и способ его тестирования
JP4893064B2 (ja) * 2006-03-30 2012-03-07 富士通セミコンダクター株式会社 半導体集積回路および半導体集積回路設計方法
JP2010266417A (ja) * 2009-05-18 2010-11-25 Sony Corp 半導体集積回路、情報処理装置、および情報処理方法、並びにプログラム
US9429983B1 (en) 2013-09-12 2016-08-30 Advanced Processor Architectures, Llc System clock distribution in a distributed computing environment
US11042211B2 (en) 2009-08-07 2021-06-22 Advanced Processor Architectures, Llc Serially connected computing nodes in a distributed computing system
US9645603B1 (en) 2013-09-12 2017-05-09 Advanced Processor Architectures, Llc System clock distribution in a distributed computing environment
US8381031B2 (en) 2009-08-07 2013-02-19 Advanced Processor Architectures, Llc Distributed computing
US8775882B2 (en) * 2010-12-28 2014-07-08 Stmicroelectronics International N.V. Testing circuits
US9234942B2 (en) 2012-09-21 2016-01-12 Apple Inc. Transition fault testing of source synchronous interface
US9804224B2 (en) 2014-09-22 2017-10-31 Nxp Usa, Inc. Integrated circuit and method of operating an integrated circuit
CN108897647B (zh) * 2018-03-19 2021-11-05 硅谷数模半导体（北京）有限公司 测试系统、测试方法及装置
CN109188250B (zh) * 2018-10-08 2020-08-18 北方电子研究院安徽有限公司 一种能够进行静态参数测试的芯片io端口电路
EP4198529B1 (en) * 2020-08-31 2025-12-24 Huawei Technologies Co., Ltd. Chip test circuit and circuit test method
CN113190389B (zh) * 2021-04-14 2024-10-29 西安紫光国芯半导体股份有限公司 自测方法、测试装置以及计算机可读存储介质
US12277372B2 (en) * 2021-04-16 2025-04-15 Synopsys, Inc. Multi-cycle test generation and source-based simulation

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06289099A (ja) * 1993-03-30 1994-10-18 Toshiba Corp スキャン回路
JPH08240645A (ja) * 1995-03-03 1996-09-17 Advantest Corp Ｉｃの内部状態を少数ピンで読み出しテストする回路
US6145100A (en) * 1998-03-04 2000-11-07 Advanced Micro Devices, Inc. Debug interface including timing synchronization logic
US6631390B1 (en) * 2000-03-06 2003-10-07 Koninklijke Philips Electronics N.V. Method and apparatus for generating random numbers using flip-flop meta-stability
US6760873B1 (en) * 2000-09-28 2004-07-06 Lsi Logic Corporation Built-in self test for speed and timing margin for a source synchronous IO interface
US6892314B2 (en) * 2001-04-02 2005-05-10 International Business Machines Corporation Method and system of automatic delay detection and receiver adjustment for synchronous bus interface
US7000164B2 (en) * 2002-01-30 2006-02-14 Sun Microsystems, Inc. Method for scan testing and clocking dynamic domino circuits in VLSI systems using level sensitive latches and edge triggered flip flops
US7139308B2 (en) 2002-04-05 2006-11-21 Sun Microsystems, Inc. Source synchronous bus repeater
US7073111B2 (en) 2002-06-10 2006-07-04 Texas Instruments Incorporated High speed interconnect circuit test method and apparatus
DE10238710A1 (de) * 2002-08-23 2004-03-04 Metabowerke Gmbh Elektrohandwerkzeuggerät
JP4319146B2 (ja) * 2002-12-27 2009-08-26 株式会社アドバンテスト 半導体試験装置
JP2004294424A (ja) * 2003-03-12 2004-10-21 Matsushita Electric Ind Co Ltd スキャンテスト制御方法、及びスキャンテスト回路
US7228476B2 (en) * 2004-11-05 2007-06-05 Stmicroelectronics, Inc. System and method for testing integrated circuits at operational speed using high-frequency clock converter
RU2374679C2 (ru) 2005-06-10 2009-11-27 Интернэшнл Бизнес Машинз Корпорейшн Микрокомпьютер и способ его тестирования

Also Published As

Publication number Publication date
US20090119561A1 (en) 2009-05-07
ATE448517T1 (de) 2009-11-15
RU2374679C2 (ru) 2009-11-27
EP1890234A1 (en) 2008-02-20
CN100504802C (zh) 2009-06-24
JPWO2006132329A1 (ja) 2009-01-08
BRPI0611883A2 (pt) 2010-10-05
US7793183B2 (en) 2010-09-07
CN101176071A (zh) 2008-05-07
DE602006010372D1 (de) 2009-12-24
JP4701244B2 (ja) 2011-06-15
RU2007147919A (ru) 2009-07-20
EP1890234B1 (en) 2009-11-11
EP1890234A4 (en) 2008-11-05
BRPI0611883B1 (pt) 2019-07-30
WO2006132329A1 (ja) 2006-12-14

Similar Documents

Publication Publication Date Title
EP1890234A4 (en) MICROCOMPUTER AND METHOD FOR TESTING IT
BRPI0800095A (pt) dispositivo de comunicação de código de diagnóstico de veìculo, e, método para transmitir dados de diagnóstico
EP1873692A3 (en) Semiconductor device
CN103136138A (zh) 一种芯片、芯片调试方法以及芯片与外部设备通信的方法
GB2470868A (en) Receiver for recovering and retiming electromagnetically coupled data
ATE493670T1 (de) Automatischer testgeräte-selbsttest
WO2007010452A3 (en) Emulation and debug interfaces for testing an integrated circuit with an asynchronous microcontroller
EP1880350A4 (en) NON-CONTACT TYPE INTEGRATED CIRCUIT BOARD AND DATA COMMUNICATION METHOD USING MULTIPLE PROTOCOLS
DE602007004665D1 (de) Vorrichtung für bidirektionale fernablesung eines wasserzählers mittels funk zur rechnungsstellung gemäss verbrauchszeiten
WO2008123156A1 (ja) 試験装置及び電子デバイス
WO2012021332A3 (en) Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations
CN109828872A (zh) 信号测试装置及方法
TW200729636A (en) Testing device, pin electronics card, electrical machine and switch
TW200515177A (en) Switch level reliable transmission
WO2004077528A3 (en) A very small pin count ic tester
US6877121B1 (en) Boundary scan cell for testing AC coupled line using phase modulation technique
CN109765482A (zh) 一种多芯片间高速互连测试方法
WO2007100406A3 (en) Reduced pin count scan chain implementation
CY1122719T1 (el) Ραδιοσυστημα με πλεονασμο
KR101996967B1 (ko) 반도체 장치
ATE375041T1 (de) Techniken zum testen der integrität übertragener signale
TW200510987A (en) Method and related apparatus for outputting clock through data path
EP1767954A1 (en) Semiconductor integrated circuit, inspecting apparatus and semiconductor integrated circuit inspecting method
TW200737011A (en) Circuit and data carrier with radio frequency interface
US20090079462A1 (en) Semiconductor device testing apparatus

Legal Events

Date Code Title Description
B06G Technical and formal requirements: other requirements [chapter 6.7 patent gazette]

Free format text: APRESENTE TRADUCAO COMPLETA DO PEDIDO ADAPTADA AO AN 127, INCLUINDO AS FOLHAS DE DESENHOS.

B06G Technical and formal requirements: other requirements [chapter 6.7 patent gazette]

Free format text: EM ADITAMENTO A PETICAO 02008154233 APRESENTE O RESOMO EM LINGUA VERNACULA ADAPTADO AO AN 127

B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing
B04C Request for examination: application reinstated [chapter 4.3 patent gazette]
B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 30/07/2019, OBSERVADAS AS CONDICOES LEGAIS. (CO) 10 (DEZ) ANOS CONTADOS A PARTIR DE 30/07/2019, OBSERVADAS AS CONDICOES LEGAIS