BRPI0713434A2 - métodos e equipamento para gerenciamento pró-ativo de cache de endereço alvo de ramificação - Google Patents

métodos e equipamento para gerenciamento pró-ativo de cache de endereço alvo de ramificação Download PDF

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Publication number
BRPI0713434A2
BRPI0713434A2 BRPI0713434-7A BRPI0713434A BRPI0713434A2 BR PI0713434 A2 BRPI0713434 A2 BR PI0713434A2 BR PI0713434 A BRPI0713434 A BR PI0713434A BR PI0713434 A2 BRPI0713434 A2 BR PI0713434A2
Authority
BR
Brazil
Prior art keywords
bypass
target address
address cache
proactive
equipment
Prior art date
Application number
BRPI0713434-7A
Other languages
English (en)
Inventor
Rychlik Bohuslav
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of BRPI0713434A2 publication Critical patent/BRPI0713434A2/pt

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3848—Speculative instruction execution using hybrid branch prediction, e.g. selection between prediction techniques
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

MéTODOS E EQUIPAMENTO PARA GERENCIAMENTO PRó-ATIVO DE CACHE DE ENDEREçO ALVO DE RAMIFICAçãO. é revelado um sistema de predição de desvio de vários estágios que inclui um cache de endereço alvo de ramificação (BTAC) e um circuito de preditor de desvio. O BTAC é configurado para armazenar uma entrada de BTAC. O circuito de preditor de desvio é configurado para armazenar informações sobre estado(s). o circuito de preditor de desvio utiliza as informações sobre estado(s) para predizer a direção de uma instrução de desvio e para gerenciar a entrada de BTAC com base nas informações sobre estado(s) armazenadas em resposta à resolução atual da instrução de desvio.
BRPI0713434-7A 2006-06-29 2007-06-28 métodos e equipamento para gerenciamento pró-ativo de cache de endereço alvo de ramificação BRPI0713434A2 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/427,349 2006-06-29
US11/427,349 US8935517B2 (en) 2006-06-29 2006-06-29 System and method for selectively managing a branch target address cache of a multiple-stage predictor
PCT/US2007/072317 WO2008003019A2 (en) 2006-06-29 2007-06-28 Methods and apparatus for proactive branch target address cache management

Publications (1)

Publication Number Publication Date
BRPI0713434A2 true BRPI0713434A2 (pt) 2012-03-13

Family

ID=38846531

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0713434-7A BRPI0713434A2 (pt) 2006-06-29 2007-06-28 métodos e equipamento para gerenciamento pró-ativo de cache de endereço alvo de ramificação

Country Status (12)

Country Link
US (2) US8935517B2 (pt)
EP (2) EP2035921B1 (pt)
JP (4) JP5558814B2 (pt)
KR (1) KR101074621B1 (pt)
CN (1) CN101479700B (pt)
BR (1) BRPI0713434A2 (pt)
CA (1) CA2654231A1 (pt)
ES (1) ES2386478T3 (pt)
MX (1) MX2008016116A (pt)
RU (1) RU2421783C2 (pt)
TW (1) TWI386850B (pt)
WO (1) WO2008003019A2 (pt)

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US10353819B2 (en) * 2016-06-24 2019-07-16 Qualcomm Incorporated Next line prefetchers employing initial high prefetch prediction confidence states for throttling next line prefetches in a processor-based system
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US20260010373A1 (en) * 2024-07-02 2026-01-08 Qualcomm Incorporated Memory prefetch mechanism based on instruction sets

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Also Published As

Publication number Publication date
JP2015144001A (ja) 2015-08-06
ES2386478T3 (es) 2012-08-21
US20120042155A1 (en) 2012-02-16
US20080005543A1 (en) 2008-01-03
WO2008003019A2 (en) 2008-01-03
EP2035921B1 (en) 2012-06-06
EP2434393B1 (en) 2017-12-20
WO2008003019A3 (en) 2008-05-02
KR101074621B1 (ko) 2011-10-17
US8935517B2 (en) 2015-01-13
JP5558814B2 (ja) 2014-07-23
TW200816046A (en) 2008-04-01
EP2434393A1 (en) 2012-03-28
JP2013229038A (ja) 2013-11-07
RU2009102809A (ru) 2010-08-10
US8782383B2 (en) 2014-07-15
TWI386850B (zh) 2013-02-21
CN101479700A (zh) 2009-07-08
JP2017107578A (ja) 2017-06-15
CN101479700B (zh) 2015-06-03
MX2008016116A (es) 2009-01-20
RU2421783C2 (ru) 2011-06-20
CA2654231A1 (en) 2008-01-03
KR20090031751A (ko) 2009-03-27
JP2009543223A (ja) 2009-12-03
EP2035921A2 (en) 2009-03-18

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 9A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: EM VIRTUDE DO ARQUIVAMENTO PUBLICADO NA RPI 2385 DE 20-09-2016 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDO O ARQUIVAMENTO DO PEDIDO DE PATENTE, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.