BRPI0820983A8 - aperfeiçoando estabilidade de leitura de memória usando pré-carga seletiva de seções de linha de bits - Google Patents

aperfeiçoando estabilidade de leitura de memória usando pré-carga seletiva de seções de linha de bits

Info

Publication number
BRPI0820983A8
BRPI0820983A8 BRPI0820983A BRPI0820983A BRPI0820983A8 BR PI0820983 A8 BRPI0820983 A8 BR PI0820983A8 BR PI0820983 A BRPI0820983 A BR PI0820983A BR PI0820983 A BRPI0820983 A BR PI0820983A BR PI0820983 A8 BRPI0820983 A8 BR PI0820983A8
Authority
BR
Brazil
Prior art keywords
bit line
line voltage
preload
sections
improving memory
Prior art date
Application number
BRPI0820983A
Other languages
English (en)
Inventor
Chen Man
H Abu-Rahma Mohamed
Chaba Ritu
Seung Yoon Sei
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BRPI0820983A2 publication Critical patent/BRPI0820983A2/pt
Publication of BRPI0820983A8 publication Critical patent/BRPI0820983A8/pt
Publication of BRPI0820983B1 publication Critical patent/BRPI0820983B1/pt
Publication of BRPI0820983B8 publication Critical patent/BRPI0820983B8/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)

Abstract

aperfeiçoando estabilidade de leitura de memória usando pré-carga seletiva um dispositivo de memória utiliza pré-carga seletiva e compartilhamento de carga para reduzir uma tensão de linha de bits antes de acessar uma célula de bits. uma redução na tensão de linha de bits é alcançada pré-carregando diferentes seções da linha de bits para tensões diferentes (por exemplo, uma tensão de alimentação e terra) e usando compartilhamento de carga entre essas seções. estabilidade de leitura melhora como um resultado da redução de tensão de linha de bits. a diferença de capacidade relativa (b2-c2) entre seções de linha de bits determina a tensão de linha de bits depois de compartilhar carga. assim, o dispositivo de memória é tolerante ao processo ou às variações de temperatura. a tensão de linha de bits pode ser controlada em projeto selecionando as seções que são pré-carregadas para tensão de alimentação ou terra.
BRPI0820983A 2007-12-15 2008-12-15 aperfeiçoando estabilidade de leitura de memória usando pré-carga seletiva de seções de linha de bits BRPI0820983B8 (pt)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US1403807P 2007-12-15 2007-12-15
US61/014,038 2007-12-15
US12/334,817 2008-12-15
PCT/US2008/086829 WO2009079455A1 (en) 2007-12-15 2008-12-15 Improving memory read stability using selective precharge of bit line sections
US12/334,817 US8223567B2 (en) 2007-12-15 2008-12-15 Memory read stability using selective precharge

Publications (4)

Publication Number Publication Date
BRPI0820983A2 BRPI0820983A2 (pt) 2015-10-13
BRPI0820983A8 true BRPI0820983A8 (pt) 2019-02-05
BRPI0820983B1 BRPI0820983B1 (pt) 2019-06-25
BRPI0820983B8 BRPI0820983B8 (pt) 2021-08-10

Family

ID=40456819

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0820983A BRPI0820983B8 (pt) 2007-12-15 2008-12-15 aperfeiçoando estabilidade de leitura de memória usando pré-carga seletiva de seções de linha de bits

Country Status (10)

Country Link
US (1) US8223567B2 (pt)
EP (1) EP2243140B1 (pt)
JP (2) JP5855342B2 (pt)
KR (1) KR101251360B1 (pt)
CN (1) CN101919003A (pt)
BR (1) BRPI0820983B8 (pt)
CA (1) CA2709400C (pt)
MX (1) MX2010006666A (pt)
RU (1) RU2444073C1 (pt)
WO (1) WO2009079455A1 (pt)

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RU2444073C1 (ru) * 2007-12-15 2012-02-27 Квэлкомм Инкорпорейтед Улучшение устойчивости считывания памяти с использованием избирательной предварительной зарядки
US7881137B2 (en) * 2008-10-23 2011-02-01 Qualcomm Incorporated Read assist for memory circuits with different precharge voltage levels for bit line pair
US8208290B2 (en) * 2009-08-26 2012-06-26 Qualcomm Incorporated System and method to manufacture magnetic random access memory
US8375173B2 (en) * 2009-10-09 2013-02-12 Qualcomm Incorporated Accessing a multi-channel memory system having non-uniform page sizes
US8279659B2 (en) * 2009-11-12 2012-10-02 Qualcomm Incorporated System and method of operating a memory device
US9385308B2 (en) 2010-03-26 2016-07-05 Qualcomm Incorporated Perpendicular magnetic tunnel junction structure
US8339882B2 (en) * 2010-07-12 2012-12-25 Promos Technologies Pte. Ltd. Dual bit line precharge architecture and method for low power dynamic random access memory (DRAM) integrated circuit devices and devices incorporating embedded DRAM
KR101781616B1 (ko) 2010-07-16 2017-09-26 삼성전자주식회사 어시스트 회로를 포함하는 스태틱 랜덤 액세스 메모리 장치
US9014749B2 (en) 2010-08-12 2015-04-21 Qualcomm Incorporated System and method to initiate a housekeeping operation at a mobile device
US8638590B2 (en) 2010-09-28 2014-01-28 Qualcomm Incorporated Resistance based memory having two-diode access device
JP5760829B2 (ja) * 2011-08-09 2015-08-12 富士通セミコンダクター株式会社 スタティックｒａｍ
US8582380B2 (en) 2011-12-21 2013-11-12 Micron Technology, Inc. Systems, circuits, and methods for charge sharing
WO2013100982A1 (en) * 2011-12-28 2013-07-04 Intel Corporation Apparatus and method for improving power delivery in a memory, such as, a random access memory
US8861285B2 (en) 2012-02-09 2014-10-14 Micron Technology, Inc. Apparatuses and methods for line charge sharing
US9224453B2 (en) * 2013-03-13 2015-12-29 Qualcomm Incorporated Write-assisted memory with enhanced speed
US9123430B2 (en) * 2013-06-14 2015-09-01 Sandisk 3D Llc Differential current sense amplifier and method for non-volatile memory
US9508405B2 (en) 2013-10-03 2016-11-29 Stmicroelectronics International N.V. Method and circuit to enable wide supply voltage difference in multi-supply memory
KR102173431B1 (ko) * 2014-05-02 2020-11-03 삼성전자주식회사 동작 전류가 감소된 메모리 장치
GB2525904B (en) 2014-05-08 2018-05-09 Surecore Ltd Memory unit
US9672898B1 (en) 2016-08-15 2017-06-06 Samsung Electronics Co., Ltd. Read column select negative boost driver circuit, system, and method
US10431278B2 (en) * 2017-08-14 2019-10-01 Qualcomm Incorporated Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature
CN109817260B (zh) * 2017-11-20 2021-02-09 中芯国际集成电路制造(上海)有限公司 位线预置电路、读操作电路、sram和方法
JP7236574B2 (ja) * 2018-02-27 2023-03-09 ラピスセミコンダクタ株式会社 半導体装置及び半導体メモリのデータ読出方法
CN108665931B (zh) * 2018-05-21 2021-04-13 上海华力集成电路制造有限公司 位线预降压器
US10657089B2 (en) 2018-07-30 2020-05-19 Texas Instruments Incorporated Embedded universal serial bus 2 repeater
US11386036B2 (en) * 2018-08-06 2022-07-12 Texas Instruments Incorporated Embedded universal serial bus 2 repeater
US11100964B1 (en) 2020-02-10 2021-08-24 Taiwan Semiconductor Manufacturing Company Limited Multi-stage bit line pre-charge
US11532351B2 (en) * 2020-05-08 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device with additional write bit lines

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JPH0821236B2 (ja) * 1987-01-26 1996-03-04 株式会社日立製作所 半導体記憶装置
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US7881137B2 (en) * 2008-10-23 2011-02-01 Qualcomm Incorporated Read assist for memory circuits with different precharge voltage levels for bit line pair

Also Published As

Publication number Publication date
EP2243140B1 (en) 2018-06-06
JP5855342B2 (ja) 2016-02-09
RU2444073C1 (ru) 2012-02-27
BRPI0820983B8 (pt) 2021-08-10
CA2709400A1 (en) 2009-06-25
CA2709400C (en) 2013-12-17
JP2015207336A (ja) 2015-11-19
US20090154274A1 (en) 2009-06-18
EP2243140A1 (en) 2010-10-27
MX2010006666A (es) 2010-09-07
CN101919003A (zh) 2010-12-15
JP2011507139A (ja) 2011-03-03
KR101251360B1 (ko) 2013-04-05
KR20100092971A (ko) 2010-08-23
WO2009079455A1 (en) 2009-06-25
RU2010129245A (ru) 2012-01-20
BRPI0820983B1 (pt) 2019-06-25
BRPI0820983A2 (pt) 2015-10-13
US8223567B2 (en) 2012-07-17

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Legal Events

Date Code Title Description
B06T Formal requirements before examination [chapter 6.20 patent gazette]
B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B15K Others concerning applications: alteration of classification

Free format text: A CLASSIFICACAO ANTERIOR ERA: G11C 7/12

Ipc: G11C 7/12 (2000.01), G11C 11/419 (1990.01), G11C 7

B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 25/06/2019, OBSERVADAS AS CONDICOES LEGAIS. (CO) 10 (DEZ) ANOS CONTADOS A PARTIR DE 25/06/2019, OBSERVADAS AS CONDICOES LEGAIS

B16C Correction of notification of the grant [chapter 16.3 patent gazette]

Free format text: REF. RPI 2529 DE 25/06/2019 QUANTO AO INVENTOR.