CA1053376A - Simplified complementary transistor process for making enhanced gain lateral transistor - Google Patents

Simplified complementary transistor process for making enhanced gain lateral transistor

Info

Publication number
CA1053376A
CA1053376A CA266,527A CA266527A CA1053376A CA 1053376 A CA1053376 A CA 1053376A CA 266527 A CA266527 A CA 266527A CA 1053376 A CA1053376 A CA 1053376A
Authority
CA
Canada
Prior art keywords
transistors
transistor
buried layers
epitaxial layer
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA266,527A
Other languages
English (en)
French (fr)
Inventor
Igor Antipov
Harry C. Calhoun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1053376A publication Critical patent/CA1053376A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/63Combinations of vertical and lateral BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0112Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0119Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs
    • H10D84/0121Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs the complementary BJTs being vertical BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/15Diffusion of dopants within, into or out of semiconductor bodies or layers from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/031Manufacture or treatment of isolation regions comprising PN junctions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/30Isolation regions comprising PN junctions

Landscapes

  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
CA266,527A 1975-11-24 1976-11-24 Simplified complementary transistor process for making enhanced gain lateral transistor Expired CA1053376A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US63496475A 1975-11-24 1975-11-24

Publications (1)

Publication Number Publication Date
CA1053376A true CA1053376A (en) 1979-04-24

Family

ID=24545858

Family Applications (1)

Application Number Title Priority Date Filing Date
CA266,527A Expired CA1053376A (en) 1975-11-24 1976-11-24 Simplified complementary transistor process for making enhanced gain lateral transistor

Country Status (5)

Country Link
JP (1) JPS5264882A (it)
CA (1) CA1053376A (it)
DE (1) DE2651449A1 (it)
FR (1) FR2347777A1 (it)
IT (1) IT1070023B (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4196440A (en) * 1978-05-25 1980-04-01 International Business Machines Corporation Lateral PNP or NPN with a high gain
FR2457564A1 (fr) * 1979-05-23 1980-12-19 Thomson Csf Transistor pnp pour circuit integre bipolaire et son procede de fabrication
US4339767A (en) * 1980-05-05 1982-07-13 International Business Machines Corporation High performance PNP and NPN transistor structure
US5279987A (en) * 1991-10-31 1994-01-18 International Business Machines Corporation Fabricating planar complementary patterned subcollectors with silicon epitaxial layer

Also Published As

Publication number Publication date
IT1070023B (it) 1985-03-25
FR2347777A1 (fr) 1977-11-04
JPS5264882A (en) 1977-05-28
DE2651449A1 (de) 1977-05-26

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