CA1145477A - Methode de fonctionnement synchrone pour processeur duplex - Google Patents
Methode de fonctionnement synchrone pour processeur duplexInfo
- Publication number
- CA1145477A CA1145477A CA000334917A CA334917A CA1145477A CA 1145477 A CA1145477 A CA 1145477A CA 000334917 A CA000334917 A CA 000334917A CA 334917 A CA334917 A CA 334917A CA 1145477 A CA1145477 A CA 1145477A
- Authority
- CA
- Canada
- Prior art keywords
- processor
- data
- processing
- accident
- trouble
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2097—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements maintaining the standby controller/processing unit updated
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
- G06F11/2038—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11030378A JPS5537641A (en) | 1978-09-08 | 1978-09-08 | Synchronization system for doubled processor |
| JP110303/78 | 1978-09-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1145477A true CA1145477A (fr) | 1983-04-26 |
Family
ID=14532271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000334917A Expired CA1145477A (fr) | 1978-09-08 | 1979-08-31 | Methode de fonctionnement synchrone pour processeur duplex |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5537641A (fr) |
| CA (1) | CA1145477A (fr) |
| DE (1) | DE2935841C2 (fr) |
| FR (1) | FR2435757B1 (fr) |
| GB (1) | GB2032149B (fr) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4823256A (en) * | 1984-06-22 | 1989-04-18 | American Telephone And Telegraph Company, At&T Bell Laboratories | Reconfigurable dual processor system |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4374414A (en) * | 1980-06-26 | 1983-02-15 | Gte Automatic Electric Labs Inc. | Arbitration controller providing for access of a common resource by a duplex plurality of central processing units |
| US4394728A (en) * | 1980-06-26 | 1983-07-19 | Gte Automatic Electric Labs Inc. | Allocation controller providing for access of multiple common resources by a duplex plurality of central processing units |
| US4395753A (en) * | 1980-06-26 | 1983-07-26 | Gte Automatic Electric Labs Inc. | Allocation controller providing for access of multiple common resources by a plurality of central processing units |
| US4363096A (en) * | 1980-06-26 | 1982-12-07 | Gte Automatic Electric Labs Inc. | Arbitration controller providing for access of a common resource by a duplex plurality of central processing units |
| US4590554A (en) * | 1982-11-23 | 1986-05-20 | Parallel Computers Systems, Inc. | Backup fault tolerant computer system |
| GB8310003D0 (en) * | 1983-04-13 | 1983-05-18 | Gen Electric Co Plc | Input signal handling apparatus |
| FR2551897A1 (fr) * | 1983-09-13 | 1985-03-15 | Westinghouse Electric Corp | Appareil et procede pour realiser la redondance dans un systeme de commande de procede, distribue |
| GB2237904B (en) * | 1984-02-28 | 1991-10-02 | Lucas Ind Plc | Digital control system |
| JPH06100201B2 (ja) * | 1984-07-16 | 1994-12-12 | 石川島播磨重工業株式会社 | 電気油圧サ−ボ制御装置 |
| EP0211063A4 (fr) * | 1985-01-22 | 1989-02-23 | Nat Can Corp | Systeme redondant de commande pour machine automatique de formage. |
| US4665520A (en) * | 1985-02-01 | 1987-05-12 | International Business Machines Corporation | Optimistic recovery in a distributed processing system |
| US5067080A (en) * | 1985-04-11 | 1991-11-19 | Lucas Industries Public Limited Company | Digital control system |
| DE3518105A1 (de) * | 1985-05-21 | 1986-11-27 | Alfred Teves Gmbh, 6000 Frankfurt | Verfahren und schaltungsanordnung zur unterdrueckung von kurzzeitigen stoerungen |
| US5155678A (en) * | 1985-10-29 | 1992-10-13 | International Business Machines Corporation | Data availability in restartable data base system |
| US4847749A (en) * | 1986-06-13 | 1989-07-11 | International Business Machines Corporation | Job interrupt at predetermined boundary for enhanced recovery |
| US5079740A (en) * | 1987-01-12 | 1992-01-07 | Ncr Corporation | System and method of providing an automatic back-up primary terminal for a cluster of secondary terminals |
| GB2217487B (en) * | 1988-04-13 | 1992-09-23 | Yokogawa Electric Corp | Dual computer system |
| US4959768A (en) * | 1989-01-23 | 1990-09-25 | Honeywell Inc. | Apparatus for tracking predetermined data for updating a secondary data base |
| US4958270A (en) * | 1989-01-23 | 1990-09-18 | Honeywell Inc. | Method for control data base updating of a redundant processor in a process control system |
| JP2960560B2 (ja) | 1991-02-28 | 1999-10-06 | 株式会社日立製作所 | 超小型電子機器 |
| JP3047275B2 (ja) * | 1993-06-11 | 2000-05-29 | 株式会社日立製作所 | バックアップ切り換え制御方法 |
| US5649089A (en) * | 1994-11-30 | 1997-07-15 | Motorola, Inc. | Method and apparatus for maintaining a redundant database system |
| EP1185928A1 (fr) | 1998-12-16 | 2002-03-13 | Kent Ridge Digital Labs | Environnement de calcul oriente processus |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1163859A (en) * | 1968-07-19 | 1969-09-10 | Ibm | Data Processing Systems |
| JPS5918740B2 (ja) * | 1976-04-27 | 1984-04-28 | 株式会社東芝 | 複数計算機システム |
| US4070630A (en) * | 1976-05-03 | 1978-01-24 | Motorola Inc. | Data transfer synchronizing circuit |
-
1978
- 1978-09-08 JP JP11030378A patent/JPS5537641A/ja active Pending
-
1979
- 1979-08-30 GB GB7930110A patent/GB2032149B/en not_active Expired
- 1979-08-31 CA CA000334917A patent/CA1145477A/fr not_active Expired
- 1979-09-05 DE DE2935841A patent/DE2935841C2/de not_active Expired
- 1979-09-07 FR FR7922466A patent/FR2435757B1/fr not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4823256A (en) * | 1984-06-22 | 1989-04-18 | American Telephone And Telegraph Company, At&T Bell Laboratories | Reconfigurable dual processor system |
Also Published As
| Publication number | Publication date |
|---|---|
| DE2935841C2 (de) | 1985-09-19 |
| FR2435757B1 (fr) | 1986-09-26 |
| DE2935841A1 (de) | 1980-07-24 |
| GB2032149B (en) | 1983-03-23 |
| JPS5537641A (en) | 1980-03-15 |
| FR2435757A1 (fr) | 1980-04-04 |
| GB2032149A (en) | 1980-04-30 |
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|---|---|---|
| CA1145477A (fr) | Methode de fonctionnement synchrone pour processeur duplex | |
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| JPS60201453A (ja) | 記憶装置アクセス制御方式 | |
| JPS6367702B2 (fr) | ||
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| JPS6217879Y2 (fr) | ||
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| BG97671A (en) | Multicomputer system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry | ||
| MKEX | Expiry |
Effective date: 20000426 |