CA1312960C - Systeme de traitement en faisceau massivement parallele - Google Patents

Systeme de traitement en faisceau massivement parallele

Info

Publication number
CA1312960C
CA1312960C CA000559528A CA559528A CA1312960C CA 1312960 C CA1312960 C CA 1312960C CA 000559528 A CA000559528 A CA 000559528A CA 559528 A CA559528 A CA 559528A CA 1312960 C CA1312960 C CA 1312960C
Authority
CA
Canada
Prior art keywords
address
signal
data
control
asserted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA000559528A
Other languages
English (en)
Inventor
Robert S. Grondalski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of CA1312960C publication Critical patent/CA1312960C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17381—Two dimensional, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
CA000559528A 1987-02-25 1988-02-23 Systeme de traitement en faisceau massivement parallele Expired - Fee Related CA1312960C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US018,937 1987-02-24
US1893787A 1987-02-25 1987-02-25

Publications (1)

Publication Number Publication Date
CA1312960C true CA1312960C (fr) 1993-01-19

Family

ID=21790510

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000559528A Expired - Fee Related CA1312960C (fr) 1987-02-25 1988-02-23 Systeme de traitement en faisceau massivement parallele

Country Status (3)

Country Link
EP (1) EP0303696A1 (fr)
CA (1) CA1312960C (fr)
WO (1) WO1988006764A2 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0509058A4 (en) * 1990-01-05 1993-11-18 Maspar Computer Corporation Router chip with quad-crossbar and hyperbar personalities
WO1991010200A1 (fr) * 1990-01-05 1991-07-11 Maspar Computer Corporation Systeme de memoire avec processeurs en parallele
US5280474A (en) * 1990-01-05 1994-01-18 Maspar Computer Corporation Scalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arrays
US5313590A (en) * 1990-01-05 1994-05-17 Maspar Computer Corporation System having fixedly priorized and grouped by positions I/O lines for interconnecting router elements in plurality of stages within parrallel computer
US5243699A (en) * 1991-12-06 1993-09-07 Maspar Computer Corporation Input/output system for parallel processing arrays
US6266342B1 (en) * 1998-04-08 2001-07-24 Nortel Networks Limited Adaption resource module and operating method therefor

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4051551A (en) * 1976-05-03 1977-09-27 Burroughs Corporation Multidimensional parallel access computer memory system
US4543627A (en) * 1981-12-14 1985-09-24 At&T Bell Laboratories Internal communication arrangement for a multiprocessor system
FR2569290B1 (fr) * 1984-08-14 1986-12-05 Trt Telecom Radio Electr Processeur pour le traitement de signal et structure de multitraitement hierarchisee comportant au moins un tel processeur
US4985832A (en) * 1986-09-18 1991-01-15 Digital Equipment Corporation SIMD array processing system with routing networks having plurality of switching stages to transfer messages among processors

Also Published As

Publication number Publication date
WO1988006764A3 (fr) 1988-12-15
WO1988006764A2 (fr) 1988-09-07
EP0303696A1 (fr) 1989-02-22

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Legal Events

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