CA2011235A1 - Methode de fabrication de contacts pour dispositif a semiconducteur - Google Patents

Methode de fabrication de contacts pour dispositif a semiconducteur

Info

Publication number
CA2011235A1
CA2011235A1 CA2011235A CA2011235A CA2011235A1 CA 2011235 A1 CA2011235 A1 CA 2011235A1 CA 2011235 A CA2011235 A CA 2011235A CA 2011235 A CA2011235 A CA 2011235A CA 2011235 A1 CA2011235 A1 CA 2011235A1
Authority
CA
Canada
Prior art keywords
layer
features
forming
semiconductor device
vias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2011235A
Other languages
English (en)
Other versions
CA2011235C (fr
Inventor
San-Mei Ku
Kathleen A. Perry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CA2011235A1 publication Critical patent/CA2011235A1/fr
Application granted granted Critical
Publication of CA2011235C publication Critical patent/CA2011235C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0113—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/011—Bipolar transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/124—Polycrystalline emitter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material

Landscapes

  • Bipolar Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
CA002011235A 1989-05-15 1990-03-01 Methode de fabrication de contacts pour dispositif a semiconducteur Expired - Fee Related CA2011235C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/351,993 US5010039A (en) 1989-05-15 1989-05-15 Method of forming contacts to a semiconductor device
US351,993 1989-05-15

Publications (2)

Publication Number Publication Date
CA2011235A1 true CA2011235A1 (fr) 1990-11-15
CA2011235C CA2011235C (fr) 1993-06-29

Family

ID=23383332

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002011235A Expired - Fee Related CA2011235C (fr) 1989-05-15 1990-03-01 Methode de fabrication de contacts pour dispositif a semiconducteur

Country Status (5)

Country Link
US (1) US5010039A (fr)
EP (1) EP0398834B1 (fr)
JP (1) JPH0658902B2 (fr)
CA (1) CA2011235C (fr)
DE (1) DE69023951T2 (fr)

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US5780323A (en) * 1990-04-12 1998-07-14 Actel Corporation Fabrication method for metal-to-metal antifuses incorporating a tungsten via plug
US5614756A (en) * 1990-04-12 1997-03-25 Actel Corporation Metal-to-metal antifuse with conductive
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KR100307272B1 (ko) * 1990-12-04 2002-05-01 하라 레이노스케 Mos소자제조방법
US5173438A (en) * 1991-02-13 1992-12-22 Micron Technology, Inc. Method of performing a field implant subsequent to field oxide fabrication by utilizing selective tungsten deposition to produce encroachment-free isolation
US5391503A (en) * 1991-05-13 1995-02-21 Sony Corporation Method of forming a stacked semiconductor device wherein semiconductor layers and insulating films are sequentially stacked and forming openings through such films and etchings using one of the insulating films as a mask
US5219793A (en) * 1991-06-03 1993-06-15 Motorola Inc. Method for forming pitch independent contacts and a semiconductor device having the same
EP0529717A3 (en) * 1991-08-23 1993-09-22 N.V. Philips' Gloeilampenfabrieken Method of manufacturing a semiconductor device having overlapping contacts
US5204286A (en) * 1991-10-15 1993-04-20 Micron Technology, Inc. Method of making self-aligned contacts and vertical interconnects to integrated circuits
KR950000660B1 (ko) * 1992-02-29 1995-01-27 현대전자산업 주식회사 고집적 소자용 미세콘택 형성방법
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US5739579A (en) * 1992-06-29 1998-04-14 Intel Corporation Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections
JPH0669449A (ja) * 1992-08-18 1994-03-11 Sony Corp ダイナミックｒａｍの配線構造およびその製造方法
US5480815A (en) * 1992-08-19 1996-01-02 Nec Corporation Method of manufacturing a biopolar transistor in which an emitter region is formed by impurities supplied from double layered polysilicon
JP3022689B2 (ja) * 1992-08-31 2000-03-21 日本電気株式会社 バイポーラトランジスタの製造方法
US5252517A (en) * 1992-12-10 1993-10-12 Micron Semiconductor, Inc. Method of conductor isolation from a conductive contact plug
US5338700A (en) * 1993-04-14 1994-08-16 Micron Semiconductor, Inc. Method of forming a bit line over capacitor array of memory cells
DE4309611A1 (de) * 1993-03-24 1994-09-29 Siemens Ag Herstellverfahren für ein Kontaktloch
US5498562A (en) 1993-04-07 1996-03-12 Micron Technology, Inc. Semiconductor processing methods of forming stacked capacitors
US6057219A (en) * 1994-07-01 2000-05-02 Motorola, Inc. Method of forming an ohmic contact to a III-V semiconductor material
US5565707A (en) * 1994-10-31 1996-10-15 International Business Machines Corporation Interconnect structure using a Al2 Cu for an integrated circuit chip
US5438011A (en) * 1995-03-03 1995-08-01 Micron Technology, Inc. Method of forming a capacitor using a photoresist contact sidewall having standing wave ripples
US5789764A (en) * 1995-04-14 1998-08-04 Actel Corporation Antifuse with improved antifuse material
US5587338A (en) * 1995-04-27 1996-12-24 Vanguard International Semiconductor Corporation Polysilicon contact stud process
JP3027195B2 (ja) * 1995-06-02 2000-03-27 アクテル・コーポレイション 隆起タングステンプラグ アンチヒューズ及びその製造方法
US5747383A (en) * 1995-09-05 1998-05-05 Taiwan Semiconductor Manufacturing Company Ltd Method for forming conductive lines and stacked vias
US5897372A (en) * 1995-11-01 1999-04-27 Micron Technology, Inc. Formation of a self-aligned integrated circuit structure using silicon-rich nitride as a protective layer
JPH09205185A (ja) * 1996-01-26 1997-08-05 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
US6083831A (en) * 1996-03-26 2000-07-04 Micron Technology, Inc. Semiconductor processing method of forming a contact pedestal, of forming a storage node of a capacitor
EP0912996B1 (fr) * 1996-07-18 2002-01-02 Advanced Micro Devices, Inc. Utilisation dans circuit integre d'un arret de gravure pour produire des lignes d'interconnexion decalees
US5854515A (en) * 1996-07-23 1998-12-29 Advanced Micro Devices, Inc. Integrated circuit having conductors of enhanced cross-sectional area
US5847462A (en) * 1996-11-14 1998-12-08 Advanced Micro Devices, Inc. Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer
JP3120750B2 (ja) * 1997-03-14 2000-12-25 日本電気株式会社 半導体装置およびその製造方法
JP3638778B2 (ja) * 1997-03-31 2005-04-13 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
US5989957A (en) * 1997-05-21 1999-11-23 Advanced Micro Devices Process for fabricating semiconductor memory device with high data retention including silicon oxynitride etch stop layer formed at high temperature with low hydrogen ion concentration
US5972749A (en) * 1998-01-05 1999-10-26 Advanced Micro Devices, Inc. Method for preventing P1 punchthrough
US6121126A (en) 1998-02-25 2000-09-19 Micron Technologies, Inc. Methods and structures for metal interconnections in integrated circuits
US6143655A (en) 1998-02-25 2000-11-07 Micron Technology, Inc. Methods and structures for silver interconnections in integrated circuits
US6492694B2 (en) 1998-02-27 2002-12-10 Micron Technology, Inc. Highly conductive composite polysilicon gate for CMOS integrated circuits
US6846739B1 (en) * 1998-02-27 2005-01-25 Micron Technology, Inc. MOCVD process using ozone as a reactant to deposit a metal oxide barrier layer
JP3515363B2 (ja) * 1998-03-24 2004-04-05 株式会社東芝 半導体装置の製造方法
US6815303B2 (en) * 1998-04-29 2004-11-09 Micron Technology, Inc. Bipolar transistors with low-resistance emitter contacts
JP2000150652A (ja) * 1998-09-03 2000-05-30 Seiko Epson Corp 半導体装置およびその製造方法
JP3528665B2 (ja) 1998-10-20 2004-05-17 セイコーエプソン株式会社 半導体装置の製造方法
US6365489B1 (en) * 1999-06-15 2002-04-02 Micron Technology, Inc. Creation of subresolution features via flow characteristics
US6211059B1 (en) * 1999-10-29 2001-04-03 Nec Corporation Method of manufacturing semiconductor device having contacts with different depths
US6358785B1 (en) * 2000-06-06 2002-03-19 Lucent Technologies, Inc. Method for forming shallow trench isolation structures
US6809398B2 (en) 2000-12-14 2004-10-26 Actel Corporation Metal-to-metal antifuse structure and fabrication method
US6972237B2 (en) * 2003-12-01 2005-12-06 Chartered Semiconductor Manufacturing Ltd. Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth
US7135753B2 (en) * 2003-12-05 2006-11-14 International Rectifier Corporation Structure and method for III-nitride monolithic power IC
US7306552B2 (en) * 2004-12-03 2007-12-11 Samsung Electronics Co., Ltd. Semiconductor device having load resistor and method of fabricating the same
US7678593B1 (en) 2006-09-06 2010-03-16 The United States of America, as represented by the Director, National Security Agency Method of fabricating optical device using multiple sacrificial spacer layers
US9059138B2 (en) 2012-01-25 2015-06-16 International Business Machines Corporation Heterojunction bipolar transistor with reduced sub-collector length, method of manufacture and design structure

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FR2508704B1 (fr) * 1981-06-26 1985-06-07 Thomson Csf Procede de fabrication de transistors bipolaires integres de tres petites dimensions
JPS6044829B2 (ja) * 1982-03-18 1985-10-05 富士通株式会社 半導体装置の製造方法
JPS59214239A (ja) * 1983-05-16 1984-12-04 Fujitsu Ltd 半導体装置の製造方法
US4465552A (en) * 1983-08-11 1984-08-14 Allied Corporation Method of selectively etching silicon dioxide with SF6 /nitriding component gas
US4686000A (en) * 1985-04-02 1987-08-11 Heath Barbara A Self-aligned contact process
US4624739A (en) * 1985-08-09 1986-11-25 International Business Machines Corporation Process using dry etchant to avoid mask-and-etch cycle
US4789648A (en) * 1985-10-28 1988-12-06 International Business Machines Corporation Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
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EP0286708B1 (fr) * 1987-04-16 1992-01-22 International Business Machines Corporation Méthode pour fabriquer des trous de contact dans une couche d'isolation double
EP0362571A3 (fr) * 1988-10-07 1990-11-28 International Business Machines Corporation Procédé de fabrication de dispositifs semi-conducteurs

Also Published As

Publication number Publication date
CA2011235C (fr) 1993-06-29
EP0398834A2 (fr) 1990-11-22
DE69023951T2 (de) 1996-06-20
DE69023951D1 (de) 1996-01-18
JPH0319213A (ja) 1991-01-28
EP0398834B1 (fr) 1995-12-06
US5010039A (en) 1991-04-23
JPH0658902B2 (ja) 1994-08-03
EP0398834A3 (fr) 1991-05-08

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