JPS6450548A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6450548A
JPS6450548A JP20652587A JP20652587A JPS6450548A JP S6450548 A JPS6450548 A JP S6450548A JP 20652587 A JP20652587 A JP 20652587A JP 20652587 A JP20652587 A JP 20652587A JP S6450548 A JPS6450548 A JP S6450548A
Authority
JP
Japan
Prior art keywords
insulating film
contact hole
diffusion layer
film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20652587A
Other languages
Japanese (ja)
Inventor
Masatoshi Shiraishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP20652587A priority Critical patent/JPS6450548A/en
Publication of JPS6450548A publication Critical patent/JPS6450548A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To round the corner part of the contact hole without changing the size of the contact hole by forming, on a semiconductor substrate including a diffusion layer region, a first insulating film and a second insulating film having an etch rate larger than the first insulating film, performing an etching to form a stepped contact hole, and performing the reflow processing of the second insulating film. CONSTITUTION:When forming a contact hole for connecting a diffusion layer 2 and a wiring conductor in a semiconductor device, a first insulating film 3 is formed on a semiconductor substrate 1 including the diffusion layer 2, are thereon a second insulating film 4 having an etch rate larger than the first insulating film 3 is formed. Then, on the second insulating film 4, a film 5 as a mask having an opening in the part corresponding to the region of said diffusion layer 2 is formed by photolithography, and through the film 5 as a mask, the first and second insulating films 3, 4 are etched by a wet or dry etching method to form a contact hole having stepped sides. Thereafter, the reflow processing of the second insulating film 4 is carried out, thereby rounding the corner portions thereof.
JP20652587A 1987-08-21 1987-08-21 Manufacture of semiconductor device Pending JPS6450548A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20652587A JPS6450548A (en) 1987-08-21 1987-08-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20652587A JPS6450548A (en) 1987-08-21 1987-08-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6450548A true JPS6450548A (en) 1989-02-27

Family

ID=16524810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20652587A Pending JPS6450548A (en) 1987-08-21 1987-08-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6450548A (en)

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