CA2013248A1 - Methode et appareil de verification de cartes de circuits - Google Patents

Methode et appareil de verification de cartes de circuits

Info

Publication number
CA2013248A1
CA2013248A1 CA2013248A CA2013248A CA2013248A1 CA 2013248 A1 CA2013248 A1 CA 2013248A1 CA 2013248 A CA2013248 A CA 2013248A CA 2013248 A CA2013248 A CA 2013248A CA 2013248 A1 CA2013248 A1 CA 2013248A1
Authority
CA
Canada
Prior art keywords
circuits
test
chain
test system
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2013248A
Other languages
English (en)
Other versions
CA2013248C (fr
Inventor
Najmi T. Jarwala
Chi W. Yau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of CA2013248A1 publication Critical patent/CA2013248A1/fr
Application granted granted Critical
Publication of CA2013248C publication Critical patent/CA2013248C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/31813—Test pattern generators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
CA002013248A 1989-05-31 1990-03-28 Methode et appareil de verification de cartes de circuits Expired - Fee Related CA2013248C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US359,679 1982-03-19
US07/359,679 US5029166A (en) 1989-05-31 1989-05-31 Method and apparatus for testing circuit boards

Publications (2)

Publication Number Publication Date
CA2013248A1 true CA2013248A1 (fr) 1990-11-30
CA2013248C CA2013248C (fr) 1994-10-18

Family

ID=23414844

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002013248A Expired - Fee Related CA2013248C (fr) 1989-05-31 1990-03-28 Methode et appareil de verification de cartes de circuits

Country Status (6)

Country Link
US (1) US5029166A (fr)
EP (1) EP0400876B1 (fr)
JP (1) JP2590294B2 (fr)
KR (1) KR0176697B1 (fr)
CA (1) CA2013248C (fr)
DE (1) DE69030528T2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112345924A (zh) * 2020-10-30 2021-02-09 上海兆芯集成电路有限公司 扫描链控制电路

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US5357615A (en) * 1991-12-19 1994-10-18 Intel Corporation Addressing control signal configuration in a computer system
US5448166A (en) * 1992-01-03 1995-09-05 Hewlett-Packard Company Powered testing of mixed conventional/boundary-scan logic
US5260649A (en) * 1992-01-03 1993-11-09 Hewlett-Packard Company Powered testing of mixed conventional/boundary-scan logic
TW253097B (fr) * 1992-03-02 1995-08-01 At & T Corp
US5231314A (en) * 1992-03-02 1993-07-27 National Semiconductor Corporation Programmable timing circuit for integrated circuit device with test access port
US5285152A (en) * 1992-03-23 1994-02-08 Ministar Peripherals International Limited Apparatus and methods for testing circuit board interconnect integrity
EP0570067B1 (fr) * 1992-05-11 2001-08-08 Jtag Technologies B.V. Dispositif de commande pour la commande d'interface entre une machine de test et un ensemble de circuits électroniques à plusieurs canaux, notamment selon la norme dite de "Boundary Test"
US5471481A (en) * 1992-05-18 1995-11-28 Sony Corporation Testing method for electronic apparatus
JPH0666884A (ja) * 1992-08-14 1994-03-11 Fujitsu Ltd 異なるスキャン系を持つｌｓｉのスキャン系接続方式
GB9217728D0 (en) * 1992-08-20 1992-09-30 Texas Instruments Ltd Method of testing interconnections between integrated circuits in a circuit
US5448576A (en) * 1992-10-29 1995-09-05 Bull Hn Information Systems Inc. Boundary scan architecture extension
US5627842A (en) * 1993-01-21 1997-05-06 Digital Equipment Corporation Architecture for system-wide standardized intra-module and inter-module fault testing
US5444716A (en) * 1993-08-30 1995-08-22 At&T Corp. Boundary-scan-based system and method for test and diagnosis
US5617531A (en) * 1993-11-02 1997-04-01 Motorola, Inc. Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor
DE4340899A1 (de) * 1993-12-01 1995-06-08 Philips Patentverwaltung Meßvorrichtung zum Testen der Verbindungen zwischen wenigstens zwei Baugruppen
EP0685074B1 (fr) * 1993-12-16 2004-03-17 Koninklijke Philips Electronics N.V. Dispositif permettant de mettre a l'essai la connexion entre une broche de sortie d'un moyen sortant une valeur logique fixe et la broche d'entree d'un circuit.
US5537052A (en) * 1994-06-17 1996-07-16 Emc Corporation System and method for executing on board diagnostics and maintaining an event history on a circuit board
US5481186A (en) * 1994-10-03 1996-01-02 At&T Corp. Method and apparatus for integrated testing of a system containing digital and radio frequency circuits
US6243843B1 (en) 1995-01-09 2001-06-05 Agilent Technologies, Inc. Post-mission test method for checking the integrity of a boundary scan test
US5574730A (en) * 1995-01-31 1996-11-12 Unisys Corporation Bussed test access port interface and method for testing and controlling system logic boards
US5862152A (en) * 1995-11-13 1999-01-19 Motorola, Inc. Hierarchically managed boundary-scan testable module and method
CA2165105C (fr) * 1995-12-13 2002-02-05 Charles Kevin Huscroft Dispositif pour controler l'integrite des chemins de transmission de donnees et les transmissions elles-memes
US6490317B1 (en) 1995-12-19 2002-12-03 Pmc-Sierra, Inc. Data, path and flow integrity monitor
US5717701A (en) * 1996-08-13 1998-02-10 International Business Machines Corporation Apparatus and method for testing interconnections between semiconductor devices
KR100277728B1 (ko) * 1997-03-13 2001-01-15 윤종용 인쇄회로기판 검사장치
US6052811A (en) * 1997-04-15 2000-04-18 Intel Corporation Method and apparatus for locating critical speed paths in integrated circuits using JTAG protocol
KR100240662B1 (ko) * 1997-09-25 2000-01-15 윤종용 제이태그에 의한 다이나믹램 테스트장치
KR19990047438A (ko) * 1997-12-04 1999-07-05 윤종용 핀 공유를 이용한 바이패스 회로를 구비하는 반도체 장치
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
GB9810512D0 (en) * 1998-05-15 1998-07-15 Sgs Thomson Microelectronics Detecting communication errors across a chip boundary
US6266793B1 (en) 1999-02-26 2001-07-24 Intel Corporation JTAG boundary scan cell with enhanced testability feature
JP3966453B2 (ja) * 1999-05-26 2007-08-29 株式会社ルネサステクノロジ 半導体集積回路
US6415409B1 (en) * 1999-11-03 2002-07-02 Unisys Corporation System for testing IC chips selectively with stored or internally generated bit streams
US6748564B1 (en) * 2000-10-24 2004-06-08 Nptest, Llc Scan stream sequencing for testing integrated circuits
US7174492B1 (en) * 2001-04-12 2007-02-06 Cisco Technology, Inc. AC coupled line testing using boundary scan test methodology
US20020194565A1 (en) * 2001-06-18 2002-12-19 Karim Arabi Simultaneous built-in self-testing of multiple identical blocks of integrated circuitry
JP2004062532A (ja) * 2002-07-29 2004-02-26 Renesas Technology Corp 接続検証装置
WO2004044601A1 (fr) * 2002-11-14 2004-05-27 Logicvision, Inc. Registre a decalage peripherique avec validation de l'etage d'attaque de plot strobee
US7278077B1 (en) * 2003-10-20 2007-10-02 Sun Microsystems, Inc. IBIST test for synchronous lines at multiple frequencies
US7496819B2 (en) * 2004-02-05 2009-02-24 Broadcom Corporation Custom logic BIST for memory controller
US7231560B2 (en) * 2004-04-16 2007-06-12 Via Technologies, Inc. Apparatus and method for testing motherboard having PCI express devices
US20070136631A1 (en) * 2005-11-19 2007-06-14 Govani Atul V Method and system for testing backplanes utilizing a boundary scan protocol
GB0526448D0 (en) * 2005-12-23 2006-02-08 Advanced Risc Mach Ltd Diagnostic mode switching
DE102006010944A1 (de) * 2006-03-09 2007-09-13 Infineon Technologies Ag Integrierter Baustein zum vereinfachten parallelen Testen, Testboard zum Testen von mehreren integrierten Bausteinen sowie Testsystem und Testereinheit
US10473717B2 (en) * 2016-11-09 2019-11-12 Texas Instruments Incorporated Methods and apparatus for test insertion points
CN115422116B (zh) * 2022-11-02 2023-03-14 井芯微电子技术(天津)有限公司 用于晶上系统jtag菊花链连接的方法和装置

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US4055801A (en) * 1970-08-18 1977-10-25 Pike Harold L Automatic electronic test equipment and method
US3772595A (en) * 1971-03-19 1973-11-13 Teradyne Inc Method and apparatus for testing a digital logic fet by monitoring currents the device develops in response to input signals
JPS5444873A (en) * 1977-09-16 1979-04-09 Toshiba Corp Controller for semiconductor measuring instrument
US4402055A (en) * 1981-01-27 1983-08-30 Westinghouse Electric Corp. Automatic test system utilizing interchangeable test devices
US4397021A (en) * 1981-06-15 1983-08-02 Westinghouse Electric Corp. Multi-processor automatic test system
US4716564A (en) * 1985-11-15 1987-12-29 Tektronix, Inc. Method for test generation
US4727545A (en) * 1986-09-02 1988-02-23 Digital Equipment Corporation Method and apparatus for isolating faults in a digital logic circuit
US4860290A (en) * 1987-06-02 1989-08-22 Texas Instruments Incorporated Logic circuit having individually testable logic modules

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112345924A (zh) * 2020-10-30 2021-02-09 上海兆芯集成电路有限公司 扫描链控制电路

Also Published As

Publication number Publication date
KR0176697B1 (ko) 1999-04-01
CA2013248C (fr) 1994-10-18
JP2590294B2 (ja) 1997-03-12
KR900018693A (ko) 1990-12-22
EP0400876A2 (fr) 1990-12-05
DE69030528T2 (de) 1997-08-07
JPH03214083A (ja) 1991-09-19
EP0400876A3 (fr) 1992-04-29
US5029166A (en) 1991-07-02
EP0400876B1 (fr) 1997-04-23
DE69030528D1 (de) 1997-05-28

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