CA2052559A1 - Dispositif de traitement vectoriel a materiel reduit - Google Patents

Dispositif de traitement vectoriel a materiel reduit

Info

Publication number
CA2052559A1
CA2052559A1 CA2052559A CA2052559A CA2052559A1 CA 2052559 A1 CA2052559 A1 CA 2052559A1 CA 2052559 A CA2052559 A CA 2052559A CA 2052559 A CA2052559 A CA 2052559A CA 2052559 A1 CA2052559 A1 CA 2052559A1
Authority
CA
Canada
Prior art keywords
indirect
vector
data
memory
vector processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2052559A
Other languages
English (en)
Other versions
CA2052559C (fr
Inventor
Koji Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2052559A1 publication Critical patent/CA2052559A1/fr
Application granted granted Critical
Publication of CA2052559C publication Critical patent/CA2052559C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8061—Details on data memory access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8076—Details on data register access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G06F9/3455—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results using stride

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
CA002052559A 1990-10-02 1991-10-01 Dispositif de traitement vectoriel a materiel reduit Expired - Fee Related CA2052559C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP264139/1990 1990-10-02
JP2264139A JP2718254B2 (ja) 1990-10-02 1990-10-02 ベクトル処理装置

Publications (2)

Publication Number Publication Date
CA2052559A1 true CA2052559A1 (fr) 1992-04-03
CA2052559C CA2052559C (fr) 1996-05-14

Family

ID=17399003

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002052559A Expired - Fee Related CA2052559C (fr) 1990-10-02 1991-10-01 Dispositif de traitement vectoriel a materiel reduit

Country Status (5)

Country Link
US (1) US5390352A (fr)
EP (1) EP0479235B1 (fr)
JP (1) JP2718254B2 (fr)
CA (1) CA2052559C (fr)
DE (1) DE69129725T2 (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04156628A (ja) * 1990-10-19 1992-05-29 Fujitsu Ltd アクセス制御方式
JPH07141327A (ja) * 1993-04-13 1995-06-02 Nec Corp ベクトル処理装置
US6282634B1 (en) * 1998-05-27 2001-08-28 Arm Limited Apparatus and method for processing data having a mixed vector/scalar register file
DE19827238B4 (de) * 1998-06-18 2004-09-30 Nec Corp. Verfahren zum Betrieb eines Vektorrechners
US7140019B2 (en) * 2002-06-28 2006-11-21 Motorola, Inc. Scheduler of program instructions for streaming vector processor having interconnected functional units
US7415601B2 (en) * 2002-06-28 2008-08-19 Motorola, Inc. Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters
US7159099B2 (en) * 2002-06-28 2007-01-02 Motorola, Inc. Streaming vector processor with reconfigurable interconnection switch
US7290122B2 (en) * 2003-08-29 2007-10-30 Motorola, Inc. Dataflow graph compression for power reduction in a vector processor
US7610466B2 (en) * 2003-09-05 2009-10-27 Freescale Semiconductor, Inc. Data processing system using independent memory and register operand size specifiers and method thereof
US7107436B2 (en) * 2003-09-08 2006-09-12 Freescale Semiconductor, Inc. Conditional next portion transferring of data stream to or from register based on subsequent instruction aspect
US7315932B2 (en) * 2003-09-08 2008-01-01 Moyer William C Data processing system having instruction specifiers for SIMD register operands and method thereof
US7275148B2 (en) * 2003-09-08 2007-09-25 Freescale Semiconductor, Inc. Data processing system using multiple addressing modes for SIMD operations and method thereof
US7184327B2 (en) * 2005-04-14 2007-02-27 Micron Technology, Inc. System and method for enhanced mode register definitions
US7945768B2 (en) * 2008-06-05 2011-05-17 Motorola Mobility, Inc. Method and apparatus for nested instruction looping using implicit predicates
US9037835B1 (en) * 2013-10-24 2015-05-19 Arm Limited Data processing method and apparatus for prefetching

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5725069A (en) * 1980-07-21 1982-02-09 Hitachi Ltd Vector data processing equipment
JPS6131502A (ja) * 1984-07-25 1986-02-14 秩父コンクリ−ト工業株式会社 路面の仕上げ方法
JPS61275954A (ja) * 1985-05-07 1986-12-06 Panafacom Ltd データ処理装置
US4745547A (en) * 1985-06-17 1988-05-17 International Business Machines Corp. Vector processing
JPS62115571A (ja) * 1985-11-15 1987-05-27 Fujitsu Ltd ベクトルアクセス制御方式
JPS62180470A (ja) * 1986-02-04 1987-08-07 Hitachi Ltd ベクトル処理装置
JPS63225837A (ja) * 1987-03-13 1988-09-20 Fujitsu Ltd 距離付きベクトルアクセス方式
JPS63251835A (ja) * 1987-04-08 1988-10-19 Hitachi Ltd ベクトル処理装置
JPS6465655A (en) * 1987-09-07 1989-03-10 Fujitsu Ltd Memory interface control system
JPH01150952A (ja) * 1987-12-08 1989-06-13 Hitachi Ltd 多次元アドレスメモリのアクセス制御方法及び装置
US4888679A (en) * 1988-01-11 1989-12-19 Digital Equipment Corporation Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements
US4949247A (en) * 1988-02-23 1990-08-14 Stellar Computer, Inc. System for transferring multiple vector data elements to and from vector memory in a single operation
US5019968A (en) * 1988-03-29 1991-05-28 Yulan Wang Three-dimensional vector processor

Also Published As

Publication number Publication date
EP0479235B1 (fr) 1998-07-08
US5390352A (en) 1995-02-14
DE69129725T2 (de) 1998-11-05
DE69129725D1 (de) 1998-08-13
EP0479235A2 (fr) 1992-04-08
JP2718254B2 (ja) 1998-02-25
EP0479235A3 (en) 1992-09-09
CA2052559C (fr) 1996-05-14
JPH04140880A (ja) 1992-05-14

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Legal Events

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