CA2202003C - Methode de production de support de silicium sur isolant (soi) par application en pate, et support de soi - Google Patents

Methode de production de support de silicium sur isolant (soi) par application en pate, et support de soi Download PDF

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Publication number
CA2202003C
CA2202003C CA002202003A CA2202003A CA2202003C CA 2202003 C CA2202003 C CA 2202003C CA 002202003 A CA002202003 A CA 002202003A CA 2202003 A CA2202003 A CA 2202003A CA 2202003 C CA2202003 C CA 2202003C
Authority
CA
Canada
Prior art keywords
substrate
silicon
soi substrate
production
soi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA002202003A
Other languages
English (en)
Other versions
CA2202003A1 (fr
Inventor
Kenji Yamagata
Takao Yonehara
Tadashi Atoji
Kiyofumi Sakaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Publication of CA2202003A1 publication Critical patent/CA2202003A1/fr
Application granted granted Critical
Publication of CA2202003C publication Critical patent/CA2202003C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Weting (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)
CA002202003A 1996-04-08 1997-04-07 Methode de production de support de silicium sur isolant (soi) par application en pate, et support de soi Expired - Fee Related CA2202003C (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP8518796 1996-04-08
JP8-085187 1996-04-08
JP9-079783 1997-03-31
JP9079783A JPH09331049A (ja) 1996-04-08 1997-03-31 貼り合わせｓｏｉ基板の作製方法及びｓｏｉ基板

Publications (2)

Publication Number Publication Date
CA2202003A1 CA2202003A1 (fr) 1997-10-08
CA2202003C true CA2202003C (fr) 2001-02-20

Family

ID=26420778

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002202003A Expired - Fee Related CA2202003C (fr) 1996-04-08 1997-04-07 Methode de production de support de silicium sur isolant (soi) par application en pate, et support de soi

Country Status (8)

Country Link
US (1) US6156624A (fr)
EP (1) EP0801420A3 (fr)
JP (1) JPH09331049A (fr)
KR (1) KR100235398B1 (fr)
CN (1) CN1099699C (fr)
CA (1) CA2202003C (fr)
SG (2) SG54491A1 (fr)
TW (1) TW337042B (fr)

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JP2005347302A (ja) 2004-05-31 2005-12-15 Canon Inc 基板の製造方法
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US7371662B2 (en) * 2006-03-21 2008-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a 3D interconnect and resulting structures
US7790565B2 (en) * 2006-04-21 2010-09-07 Corning Incorporated Semiconductor on glass insulator made using improved thinning process
JP5171016B2 (ja) 2006-10-27 2013-03-27 キヤノン株式会社 半導体部材、半導体物品の製造方法、その製造方法を用いたｌｅｄアレイ
JP2009094144A (ja) * 2007-10-04 2009-04-30 Canon Inc 発光素子の製造方法
JP2011523383A (ja) * 2008-05-23 2011-08-11 富士フイルム株式会社 基板を接合する方法及び装置
JP5796936B2 (ja) * 2010-06-01 2015-10-21 キヤノン株式会社 多孔質ガラスの製造方法
CN103400890A (zh) * 2013-07-08 2013-11-20 浙江晶科能源有限公司 一种晶硅太阳电池pecvd色差片去膜重镀的返工工艺
JP6447439B2 (ja) * 2015-09-28 2019-01-09 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP6295378B1 (ja) * 2016-11-25 2018-03-14 新電元工業株式会社 半導体装置の製造方法
JP6558355B2 (ja) 2016-12-19 2019-08-14 信越半導体株式会社 Ｓｏｉウェーハの製造方法
CN116529867A (zh) 2020-10-29 2023-08-01 美商艾德亚半导体接合科技有限公司 直接接合方法和结构
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JP3265493B2 (ja) * 1994-11-24 2002-03-11 ソニー株式会社 Ｓｏｉ基板の製造方法
KR100322585B1 (ko) 1998-10-31 2002-05-09 윤종용 인쇄기의 광주사 시스템 및 그 이미지 주사 개시시기 조정방법

Also Published As

Publication number Publication date
US6156624A (en) 2000-12-05
TW337042B (en) 1998-07-21
SG80064A1 (en) 2001-04-17
CN1099699C (zh) 2003-01-22
EP0801420A3 (fr) 1998-05-20
JPH09331049A (ja) 1997-12-22
CA2202003A1 (fr) 1997-10-08
CN1166049A (zh) 1997-11-26
SG54491A1 (en) 1998-11-16
EP0801420A2 (fr) 1997-10-15
KR100235398B1 (ko) 1999-12-15

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