CA932482A - Method of contacting a semiconductor body having a plurality of electrodes - Google Patents

Method of contacting a semiconductor body having a plurality of electrodes

Info

Publication number
CA932482A
CA932482A CA119383A CA119383A CA932482A CA 932482 A CA932482 A CA 932482A CA 119383 A CA119383 A CA 119383A CA 119383 A CA119383 A CA 119383A CA 932482 A CA932482 A CA 932482A
Authority
CA
Canada
Prior art keywords
electrodes
contacting
semiconductor body
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA119383A
Other languages
English (en)
Other versions
CA119383S (en
Inventor
Peltz Hanns-Heinz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Application granted granted Critical
Publication of CA932482A publication Critical patent/CA932482A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H10W70/042—Etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
CA119383A 1970-07-29 1971-07-29 Method of contacting a semiconductor body having a plurality of electrodes Expired CA932482A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19702037666 DE2037666A1 (de) 1970-07-29 1970-07-29 Verfahren zum Kontaktieren eines mit mehreren Elektroden versehenen Halbleiterkörpers mit Hilfe eines aus einem Metallblech hergestellten Systems von elektrischen Zuleitungen

Publications (1)

Publication Number Publication Date
CA932482A true CA932482A (en) 1973-08-21

Family

ID=5778271

Family Applications (1)

Application Number Title Priority Date Filing Date
CA119383A Expired CA932482A (en) 1970-07-29 1971-07-29 Method of contacting a semiconductor body having a plurality of electrodes

Country Status (9)

Country Link
US (1) US3795044A (de)
AT (1) AT339962B (de)
CA (1) CA932482A (de)
CH (1) CH524248A (de)
DE (1) DE2037666A1 (de)
FR (1) FR2099654B1 (de)
GB (1) GB1320619A (de)
NL (1) NL7110490A (de)
SE (1) SE361381B (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3853650A (en) * 1973-02-12 1974-12-10 Honeywell Inc Stress sensor diaphragms over recessed substrates
US4711700A (en) * 1985-07-03 1987-12-08 United Technologies Corporation Method for densifying leadframe conductor spacing
GB2178895B (en) * 1985-08-06 1988-11-23 Gen Electric Co Plc Improved preparation of fragile devices
US5205036A (en) * 1988-10-17 1993-04-27 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device with selective coating on lead frame
KR930006868A (ko) * 1991-09-11 1993-04-22 문정환 반도체 패키지
JPH05102364A (ja) * 1991-10-11 1993-04-23 Rohm Co Ltd 電子部品用リードフレームの製造方法
US5454905A (en) * 1994-08-09 1995-10-03 National Semiconductor Corporation Method for manufacturing fine pitch lead frame
JPH10116861A (ja) * 1996-10-09 1998-05-06 Texas Instr Japan Ltd キャリアテープ、及びキャリアテープ製造方法
DE10321257B4 (de) 2003-05-06 2006-04-27 Infineon Technologies Ag Optische oder optoelektronische Anordnung mit mindestens einem auf einem Metallträger angeordneten optoelektronischen Bauelement
US6815806B1 (en) * 2003-07-17 2004-11-09 International Business Machines Corp. Asymmetric partially-etched leads for finer pitch semiconductor chip package

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3390308A (en) * 1966-03-31 1968-06-25 Itt Multiple chip integrated circuit assembly
US3436810A (en) * 1967-07-17 1969-04-08 Jade Corp Method of packaging integrated circuits
US3559285A (en) * 1968-01-08 1971-02-02 Jade Corp Method of forming leads for attachment to semi-conductor devices
DE1954135A1 (de) * 1969-10-28 1971-05-06 Licentia Gmbh Verfahren zum Herstellen einer Halbleiteranordnung

Also Published As

Publication number Publication date
NL7110490A (de) 1972-02-01
GB1320619A (en) 1973-06-20
DE2037666A1 (de) 1972-02-03
US3795044A (en) 1974-03-05
AT339962B (de) 1977-11-25
FR2099654B1 (de) 1977-03-18
SE361381B (de) 1973-10-29
ATA617871A (de) 1977-03-15
FR2099654A1 (de) 1972-03-17
CH524248A (de) 1972-06-15

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