CH450554A - Verfahren zur Herstellung einer Halbleiteranordnung mit einer Mesa - Google Patents

Verfahren zur Herstellung einer Halbleiteranordnung mit einer Mesa

Info

Publication number
CH450554A
CH450554A CH1021765A CH1021765A CH450554A CH 450554 A CH450554 A CH 450554A CH 1021765 A CH1021765 A CH 1021765A CH 1021765 A CH1021765 A CH 1021765A CH 450554 A CH450554 A CH 450554A
Authority
CH
Switzerland
Prior art keywords
mesa
manufacturing
semiconductor device
semiconductor
Prior art date
Application number
CH1021765A
Other languages
English (en)
Inventor
Joachim Dipl Phys Dathe
Winstel Guenter Dr Dipl-Phys
Karl-Heinz Dipl Phys Zschauer
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of CH450554A publication Critical patent/CH450554A/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/021—Manufacture or treatment of air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/20—Air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/049—Equivalence and options
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/145—Shaped junctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/912—Displacing pn junction
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/92—Controlling diffusion profile by oxidation
CH1021765A 1964-07-21 1965-07-21 Verfahren zur Herstellung einer Halbleiteranordnung mit einer Mesa CH450554A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE1964S0092168 DE1439417B2 (de) 1964-07-21 1964-07-21 Verfahren zum herstellen einer halbleiteranordnung

Publications (1)

Publication Number Publication Date
CH450554A true CH450554A (de) 1968-01-31

Family

ID=7517035

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1021765A CH450554A (de) 1964-07-21 1965-07-21 Verfahren zur Herstellung einer Halbleiteranordnung mit einer Mesa

Country Status (9)

Country Link
US (1) US3463681A (de)
AT (1) AT260308B (de)
BE (1) BE667183A (de)
CH (1) CH450554A (de)
DE (1) DE1439417B2 (de)
FI (1) FI44431B (de)
GB (1) GB1110321A (de)
NL (1) NL6508744A (de)
SE (1) SE312178B (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3460009A (en) * 1967-12-29 1969-08-05 Westinghouse Electric Corp Constant gain power transistor
US3912556A (en) * 1971-10-27 1975-10-14 Motorola Inc Method of fabricating a scannable light emitting diode array
NL185484C (nl) * 1975-04-28 1990-04-17 Philips Nv Halfgeleiderinrichting met een halfgeleiderlichaam bevattende tenminste een transistor.
JPS5346285A (en) * 1976-10-08 1978-04-25 Hitachi Ltd Mesa type high breakdown voltage semiconductor device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2890395A (en) * 1957-10-31 1959-06-09 Jay W Lathrop Semiconductor construction
US2899344A (en) * 1958-04-30 1959-08-11 Rinse in
US2930722A (en) * 1959-02-03 1960-03-29 Bell Telephone Labor Inc Method of treating silicon
US3040218A (en) * 1959-03-10 1962-06-19 Hoffman Electronics Corp Constant current devices
US3189799A (en) * 1961-06-14 1965-06-15 Microwave Ass Semiconductor devices and method of fabricating them
US3093507A (en) * 1961-10-06 1963-06-11 Bell Telephone Labor Inc Process for coating with silicon dioxide
US3241010A (en) * 1962-03-23 1966-03-15 Texas Instruments Inc Semiconductor junction passivation
US3294600A (en) * 1962-11-26 1966-12-27 Nippon Electric Co Method of manufacture of semiconductor elements

Also Published As

Publication number Publication date
DE1439417A1 (de) 1969-03-06
FI44431B (de) 1971-08-02
AT260308B (de) 1968-02-26
NL6508744A (de) 1966-01-24
BE667183A (de) 1966-01-20
GB1110321A (en) 1968-04-18
DE1439417B2 (de) 1976-09-23
SE312178B (de) 1969-07-07
US3463681A (en) 1969-08-26

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