CN102403200A - Method for realizing pattern with line width of 0.18[mu]m by double photoetching method for I line photoetching machine - Google Patents
Method for realizing pattern with line width of 0.18[mu]m by double photoetching method for I line photoetching machine Download PDFInfo
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- CN102403200A CN102403200A CN2011103864810A CN201110386481A CN102403200A CN 102403200 A CN102403200 A CN 102403200A CN 2011103864810 A CN2011103864810 A CN 2011103864810A CN 201110386481 A CN201110386481 A CN 201110386481A CN 102403200 A CN102403200 A CN 102403200A
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- 238000001259 photo etching Methods 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 78
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000007797 corrosion Effects 0.000 claims abstract description 17
- 238000005260 corrosion Methods 0.000 claims abstract description 17
- 239000011248 coating agent Substances 0.000 claims abstract description 6
- 238000000576 coating method Methods 0.000 claims abstract description 6
- 229920005591 polysilicon Polymers 0.000 claims description 44
- 230000003628 erosive effect Effects 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000001459 lithography Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 238000011161 development Methods 0.000 abstract description 7
- 238000012937 correction Methods 0.000 abstract description 4
- 230000000873 masking effect Effects 0.000 abstract 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000012827 research and development Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000671 immersion lithography Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
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- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
The invention relates to a method for realizing a pattern with a line width of 0.18[mu]m by a double photoetching method for an I line photoetching machine, which comprises the following steps of: a, carrying out photoetching at first time, namely, coating a photoresist, using the I line photoetching machine for photoetching of the photoresist; b, carrying out corrosion treatment at first time, namely, corroding to remove polycrystalline silicon on a substrate; c, carrying out photoetching at second time for registration, namely, coating the photoresist to the surface of the substrate, and coating a masking and locating photoresist to the surface at one side of the polycrystalline silicon in contact with the photoresist, wherein the masking and locating photoresist is connected with the photoresist at one side of the polycrystalline silicon; and using the overlay offset of the I line photoetching machine for correction to make the width of the masking and locating photoresist be 0.18[mu]m; and d, carrying out corrosion treatment at second time, namely, corroding to remove the photoetched polycrystalline silicon on the substrate to obtain the polycrystalline silicon pattern with the width of 0.18[mu]m below the masking and locating photoresist. The method has simple and convenient process steps, can obtain the pattern with the line width of 0.18[mu]m by using the I line photoresist and reduce the development cost, can be suitable for the need of scientific research development, and is safe and reliable.
Description
Technical field
The present invention relates to the method for etching live width figure in a kind of integrated circuit; Especially a kind of I line mask aligner is realized the method for 0.18 μ m live width figure with two inferior photoetching processes; Specifically limit of utilization resolution is no more than the method for I linear light machine engraving at the quarter erosion formation 0.18 μ m live width figure of 0.35 μ m, belongs to the technical field of integrated circuit fabrication process.
Background technology
Along with the development of integrated circuit silicon process technology, live width is lowered into the important technology index for the silicon process technology development.Live width reduces and to mean that power consumption reduces, and chip area descends significantly, and integrated level increases substantially, and 0.18 μ m technology has also become the major technique platform of 8 cun and 12 cun FAB (foundries of chip manufacturing company) factory, and its key equipment is a mask aligner.In order to make mask aligner reach 0.18 μ m and higher resolution, the general requirement of mask aligner is 193nm LASER Light Source mask aligner, adopted RET simultaneously: such as OPC (Organic Photoconductor), and PSM, liquid immersion lithography etc.Because its high cost and higher maintaining expense, the possibility that in ordinary laboratory, has the 193nm mask aligner is lower, can not adapt to the needs of scientific research and development.
On behalf of mask aligner, mask aligner resolution: R can differentiate to such an extent that minimum bar is wide, when the size of needs exposures less than limiting resolution the time this mask aligner then can't reach requirement, just need to change more high-resolution mask aligner.Generally the computing formula of mask aligner resolution is:
k
1Be process factor, with 0.75 calculating, λ is the mask aligner optical source wavelength, and NA is the photoetching machine lens numerical aperture.
Adopt following formula calculating I line mask aligner resolution to be: 0.48 μ m, wherein NA is 0.57, I line mask aligner optical source wavelength is 365nm.Adopt following formula calculating 193nm mask aligner resolution to be: 0.15 μ m, wherein NA is 1.0, carving the machine optical source wavelength is 193nm.Through above calculating can simply draw NA be 0.57 common I line mask aligner limiting resolution about 0.5 μ m, want to reach the figure of the live width of 0.18 μ m and can't realize through conventional photoetching method, must just might accomplish through special technology.
The conventional 0.18 μ m technology photolithographic exposure step that realizes: detailed figures is seen accompanying drawing 1---Fig. 2
Step 1: photoetching (adopting 193nm wavelength limit resolution is the mask aligner of 0.13 μ m), as shown in Figure 1;
Step 2: corrosion (forming the figure of 0.18 μ m live width), and remove the photoresist on the required width polysilicon, as shown in Figure 3.
Summary of the invention
The objective of the invention is to overcome the deficiency that exists in the prior art; Provide a kind of I line mask aligner to realize the method for 0.18 μ m live width figure with two inferior photoetching processes; Its processing step is simple and convenient, utilizes I line photoresist to obtain 0.18 μ m live width figure, and can be suitable for scientific research and development needs; Reduce development cost, safe and reliable.
According to technical scheme provided by the invention, a kind of I line mask aligner uses two inferior photoetching processes to realize the method for 0.18 μ m live width figure, and said photoetching method comprises the steps:
A, photoetching for the first time: have at surface deposition on the substrate of polysilicon to apply photoresist, said photoresist is covered in the surface of polysilicon; Utilize I line mask aligner that above-mentioned photoresist is carried out photoetching, keep the photoresist of desired location;
B, corrosion for the first time: utilize the polysilicon on the above-mentioned substrate of above-mentioned photoresist erosion removal, and behind the corrosion polysilicon, remove photoresist;
C, lithography registration for the second time: on the substrate corresponding to the surface-coated photoresist behind the erosion removal polysilicon; And shelter the location photoresist at polysilicon corresponding to the side surface coating that contacts with photoresist, the said photoresist of sheltering location photoresist and polysilicon one side links into an integrated entity; Utilize I linear light mantle at quarter side-play amount at quarter to revise and make that the width of sheltering the location photoresist is 0.18 μ m;
D, corrosion for the second time: the polysilicon on the above-mentioned substrate of erosion removal after the photoetching, obtaining sheltering photoresist below, location width is the polysilicon graphics of 0.18 μ m.
The material of said substrate comprises silicon.
Advantage of the present invention: earlier cooperates post-etching to obtain corresponding polysilicon with photoresist through I line mask aligner, utilize the I linear light to carve mantle then and carve offset correction and obtain being coated on and shelter the location photoresist on the polysilicon 2, the feasible width of locating photoresist of sheltering reaches accurate 0.18 μ m; After utilization is sheltered the location photoresist is corroded polysilicon; Can on substrate, obtain 0.18 required μ m live width figure, thereby obtain required 0.18 μ m live width figure through I line mask aligner through after the corresponding steps, processing step is simple and convenient; Utilize I line photoresist to obtain 0.18 μ m live width figure; Can be suitable for scientific research and development needs, and reduces development cost, safe and reliable.
Description of drawings
Fig. 1 forms the generalized section of 0.18 μ m photoresist after for the mask aligner photoetching that is 0.13 μ m of the existing 193nm of employing wavelength limit resolution.
Fig. 2 utilizes the photoresist among Fig. 1 to corrode the back generalized section.
Fig. 3 is the generalized section after the I line mask aligner photoetching for the first time of 0.5 μ m for the present invention adopts limiting resolution.
Fig. 4 carries out the corrosion back generalized section first time for the present invention utilizes the photoresist among Fig. 3
Fig. 5 is the back generalized section after the I line mask aligner photoetching for the second time of 0.5 μ m for this aspect adopts limiting resolution.
Fig. 6 carries out the corrosion back generalized section second time for the present invention utilizes the photoresist among Fig. 5.
Description of reference numerals: 1-substrate, 2-polysilicon, 3-photoresist and 4-shelter the location photoresist.
Embodiment
Below in conjunction with concrete accompanying drawing and embodiment the present invention is described further.
Like Fig. 3～shown in Figure 6: obtain 0.18 μ m live width image in order to utilize I line mask aligner, photoetching method of the present invention comprises the steps:
A, photoetching for the first time: have at surface deposition on the substrate 1 of polysilicon 2 to apply photoresist 3, said photoresist 3 is covered in the surface of polysilicon 2; Utilize I line mask aligner that above-mentioned photoresist 3 is carried out photoetching, keep the photoresist 3 of desired location; The material of substrate 1 comprises silicon;
As shown in Figure 3: through I line mask aligner above-mentioned photoresist 3 is carried out photoetching, remove the photoresist 3 that does not need the position, keep covering desired location photoresist 3 simultaneously, the width of said reservation photoresist 3 is about 10 μ m, much larger than 0.18 μ m;
B, corrosion for the first time: utilize the polysilicon 2 on the above-mentioned substrate of above-mentioned photoresist 3 erosion removals, and remove photoresist 3 in corrosion polysilicon 2 backs;
As shown in Figure 4: as to adopt conventional etching process corrosion polysilicon 2, be not corroded as the polysilicon 2 of photoresist 3 shield portions, as the basis that forms 0.18 μ m live width figure; Photoresist 3 is removed in corrosion polysilicon 2 backs, is convenient to next step technological operation;
C, lithography registration for the second time: on the substrate 1 corresponding to the surface-coated photoresist 3 behind the erosion removal polysilicon 2; And shelter location photoresist 4 at polysilicon 2 corresponding to the side surface coating that contacts with photoresist 3, the said photoresist 3 of sheltering location photoresist 4 and polysilicon 2 one sides links into an integrated entity; Through being revised, mask aligner alignment side-play amount makes that the width of sheltering location photoresist 4 is 0.18 μ m;
As shown in Figure 5: as higher alignment precision to be arranged because the I linear light is carved facility; Said alignment precision is greater than 0.18 μ m; According to the vestige that keeps photoresist 3 after the photoetching first time; Can carve through the I linear light at polysilicon 2 and can make after mantle is carved offset correction that the width of sheltering location photoresist 4 that rides on the polysilicon 2 is 0.18 μ m, simultaneously the substrate 1 surface-coated photoresist 3 behind corrosion polysilicon 2;
D, corrosion for the second time: polycrystalline 2 silicon on the above-mentioned substrate 1 of erosion removal after the photoetching, obtaining sheltering location photoresist 4 below width is the polysilicon graphics of 0.18 μ m;
As shown in Figure 6: when locating photoresist 4 through obtaining sheltering of 0.18 μ m live width the second time after the lithography registration; Remove corresponding polysilicon 2 through conventional polysilicon etching process; Thereby can obtain corresponding polysilicon 2 in desired location; The said width that obtains polysilicon 2 is consistent with the width of sheltering location photoresist 4, is 0.18 μ m.
The present invention cooperates post-etching to obtain corresponding polysilicon 2 through I line mask aligner earlier with photoresist 3, utilize I linear light mantle at quarter offset correction at quarter to obtain being coated on sheltering on the polysilicon 2 then and locate photoresist 4, makes the width of sheltering location photoresist 4 reach accurate 0.18 μ m; After utilization is sheltered location photoresist 4 pairs of polysilicons 2 and is corroded; Can on substrate 1, obtain 0.18 required μ m live width figure, thereby obtain required 0.18 μ m live width figure through I line mask aligner through after the corresponding steps, processing step is simple and convenient; Utilize I line photoresist to obtain 0.18 μ m live width figure; Can be suitable for scientific research and development needs, and reduces development cost, safe and reliable.
Claims (2)
1. an I line mask aligner uses two inferior photoetching processes to realize the method for 0.18 μ m live width figure, and it is characterized in that: said photoetching method comprises the steps:
(a), photoetching for the first time: have the substrate (1) of polysilicon (2) to go up at surface deposition and apply photoresist (3), said photoresist (3) is covered in the surface of polysilicon (2); Utilize I line mask aligner that above-mentioned photoresist (3) is carried out photoetching, keep the photoresist (3) of desired location;
(b), corrosion for the first time: utilize the polysilicon (2) on the above-mentioned substrate of above-mentioned photoresist (3) erosion removal (1), and remove photoresist (3) in corrosion polysilicon (2) back;
(c), lithography registration for the second time: go up corresponding to the surface-coated photoresist (3) behind the erosion removal polysilicon (2) at substrate (1); And shelter location photoresist (4) at polysilicon (2) corresponding to the side surface coating that contacts with photoresist (3), the said photoresist (3) of sheltering location photoresist (4) and polysilicon (2) one sides links into an integrated entity; Utilize I linear light mantle at quarter side-play amount at quarter to revise and make that the width of sheltering location photoresist (4) is 0.18 μ m;
(d), corrosion for the second time: the above-mentioned substrate of erosion removal (1) is gone up the polysilicon (2) after the photoetching, and obtaining sheltering location photoresist (4) below width is the polysilicon graphics of 0.18 μ m.
2. I line mask aligner according to claim 1 uses two inferior photoetching processes to realize the method for 0.18 μ m live width figure, and it is characterized in that: the material of said substrate (1) comprises silicon.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201110386481 CN102403200B (en) | 2011-11-29 | 2011-11-29 | Method for realizing pattern with line width of 0.18[mu]m by double photoetching method for I line photoetching machine |
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| CN 201110386481 CN102403200B (en) | 2011-11-29 | 2011-11-29 | Method for realizing pattern with line width of 0.18[mu]m by double photoetching method for I line photoetching machine |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106933064A (en) * | 2017-03-27 | 2017-07-07 | 上海华力微电子有限公司 | Realize the photoetching process of smaller line width |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01304457A (en) * | 1988-06-02 | 1989-12-08 | Fujitsu Ltd | Pattern forming method |
| JP2006049642A (en) * | 2004-08-05 | 2006-02-16 | Sumitomo Metal Mining Package Materials Co Ltd | Method of manufacturing double-sided interconnection tape carrier and tape carrier manufactured thereby |
| CN101201544A (en) * | 2006-12-11 | 2008-06-18 | 上海华虹Nec电子有限公司 | Semiconductor photolithography method |
| CN102005382A (en) * | 2009-09-01 | 2011-04-06 | 国际商业机器公司 | Dual exposure track only pitch split process |
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- 2011-11-29 CN CN 201110386481 patent/CN102403200B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01304457A (en) * | 1988-06-02 | 1989-12-08 | Fujitsu Ltd | Pattern forming method |
| JP2006049642A (en) * | 2004-08-05 | 2006-02-16 | Sumitomo Metal Mining Package Materials Co Ltd | Method of manufacturing double-sided interconnection tape carrier and tape carrier manufactured thereby |
| CN101201544A (en) * | 2006-12-11 | 2008-06-18 | 上海华虹Nec电子有限公司 | Semiconductor photolithography method |
| CN102005382A (en) * | 2009-09-01 | 2011-04-06 | 国际商业机器公司 | Dual exposure track only pitch split process |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106933064A (en) * | 2017-03-27 | 2017-07-07 | 上海华力微电子有限公司 | Realize the photoetching process of smaller line width |
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