CN102403200B - Method for realizing pattern with line width of 0.18[mu]m by double photoetching method for I line photoetching machine - Google Patents
Method for realizing pattern with line width of 0.18[mu]m by double photoetching method for I line photoetching machine Download PDFInfo
- Publication number
- CN102403200B CN102403200B CN 201110386481 CN201110386481A CN102403200B CN 102403200 B CN102403200 B CN 102403200B CN 201110386481 CN201110386481 CN 201110386481 CN 201110386481 A CN201110386481 A CN 201110386481A CN 102403200 B CN102403200 B CN 102403200B
- Authority
- CN
- China
- Prior art keywords
- photoresist
- photoetching
- polysilicon
- substrate
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000001259 photo etching Methods 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 75
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000007797 corrosion Effects 0.000 claims abstract description 14
- 238000005260 corrosion Methods 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims description 44
- 238000001459 lithography Methods 0.000 claims description 34
- 230000003628 erosive effect Effects 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 238000011161 development Methods 0.000 abstract description 7
- 238000012937 correction Methods 0.000 abstract description 4
- 230000000873 masking effect Effects 0.000 abstract 4
- 239000011248 coating agent Substances 0.000 abstract 3
- 238000000576 coating method Methods 0.000 abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000012827 research and development Methods 0.000 description 4
- 239000003292 glue Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000671 immersion lithography Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
Images
Landscapes
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
The invention relates to a method for realizing a pattern with a line width of 0.18[mu]m by a double photoetching method for an I line photoetching machine, which comprises the following steps of: a, carrying out photoetching at first time, namely, coating a photoresist, using the I line photoetching machine for photoetching of the photoresist; b, carrying out corrosion treatment at first time, namely, corroding to remove polycrystalline silicon on a substrate; c, carrying out photoetching at second time for registration, namely, coating the photoresist to the surface of the substrate, and coating a masking and locating photoresist to the surface at one side of the polycrystalline silicon in contact with the photoresist, wherein the masking and locating photoresist is connected with the photoresist at one side of the polycrystalline silicon; and using the overlay offset of the I line photoetching machine for correction to make the width of the masking and locating photoresist be 0.18[mu]m; and d, carrying out corrosion treatment at second time, namely, corroding to remove the photoetched polycrystalline silicon on the substrate to obtain the polycrystalline silicon pattern with the width of 0.18[mu]m below the masking and locating photoresist. The method has simple and convenient process steps, can obtain the pattern with the line width of 0.18[mu]m by using the I line photoresist and reduce the development cost, can be suitable for the need of scientific research development, and is safe and reliable.
Description
Technical field
The present invention relates to the method for etching live width figure in a kind of integrated circuit, especially a kind of I Lithography machine is realized the method for 0.18 μ m live width figure with two inferior photoetching processes, specifically limit of utilization resolution is no more than the method for the I Lithography machine engraving erosion formation 0.18 μ m live width figure of 0.35 μ m, belongs to the technical field of integrated circuit fabrication process.
Background technology
Along with the development of integrated circuit silicon process technology, live width is lowered into the important technology index for the silicon process technology development.The live width reduction means power-dissipation-reduced, chip area significantly descends, integrated level increases substantially, and 0.18 μ m technology has also become the major technique platform of 8 cun and 12 cun FAB foundries of company (chip manufacturing) factory, and its key equipment is mask aligner.In order to make mask aligner reach 0.18 μ m and higher resolution, the mask aligner General Requirements is 193nm LASER Light Source mask aligner, has adopted simultaneously resolution enhance technology: such as OPC (Organic Photoconductor), PSM, liquid immersion lithography etc.Due to its high cost and higher maintaining expense, the possibility that has the 193nm mask aligner in common laboratory is lower, can not adapt to the needs of scientific research and development.
Mask aligner resolution: R is representing that mask aligner can differentiate to such an extent that minimum bar is wide, when the size of needs exposure less than limiting resolution the time this mask aligner can't reach requirement, just need to change more high-resolution mask aligner.Generally the computing formula of mask aligner resolution is:
Adopt following formula calculating I Lithography machine resolution to be: 0.48 μ m, wherein NA is that 0.57, I Lithography machine optical source wavelength is 365nm.Adopt following formula calculating 193nm mask aligner resolution to be: 0.15 μ m, wherein NA is 1.0, carving the machine optical source wavelength is 193nm.Can simply to draw NA be 0.57 common I Lithography machine limiting resolution in 0.5 μ m left and right by above calculating, wants to reach the figure of the live width of 0.18 μ m and can't realize by conventional photoetching method, must just might complete by special technique.
Routine realizes 0.18 μ m technique photolithographic exposure step: detailed figures is seen accompanying drawing 1---Fig. 2
Step 1: photoetching (adopting 193nm wavelength limit resolution is the mask aligner of 0.13 μ m), as shown in Figure 1;
Step 2: corrode (figure that forms 0.18 μ m live width), and remove the photoresist on required width polysilicon, as shown in Figure 3.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, provide a kind of I Lithography machine to realize the method for 0.18 μ m live width figure with two inferior photoetching processes, its processing step is simple and convenient, utilize I Lithography glue to obtain 0.18 μ m live width figure, can applicable scientific research and development need, reduce development cost, safe and reliable.
According to technical scheme provided by the invention, a kind of I Lithography machine is realized the method for 0.18 μ m live width figure with two inferior photoetching processes, and described photoetching method comprises the steps:
A, photoetching for the first time: have at surface deposition on the substrate of polysilicon to apply photoresist, described photoresist is covered in the surface of polysilicon; Utilize I Lithography machine to carry out photoetching to above-mentioned photoresist, keep the photoresist of desired location;
B, corrosion for the first time: utilize the polysilicon on the above-mentioned substrate of above-mentioned photoresist erosion removal, and remove photoresist after the corrosion polysilicon;
C, lithography registration for the second time: on substrate corresponding to the surface-coated photoresist after the erosion removal polysilicon, and apply corresponding to the side surface that contacts with photoresist at polysilicon and shelter the location photoresist, the described photoresist of sheltering location photoresist and polysilicon one side links into an integrated entity; Utilizing I Lithography mantle side-play amount at quarter to revise and making the width of sheltering the location photoresist is 0.18 μ m;
D, corrosion for the second time: the polysilicon on the above-mentioned substrate of erosion removal after photoetching, obtaining sheltering photoresist below, location width is the polysilicon graphics of 0.18 μ m.
The material of described substrate comprises silicon.
advantage of the present invention: first coordinate post-etching to obtain corresponding polysilicon with photoresist by I Lithography machine, then utilizing I Lithography mantle to carve offset correction obtains being coated on and shelters the location photoresist on polysilicon 2, make the width of sheltering the location photoresist reach accurate 0.18 μ m, after utilization is sheltered the location photoresist is corroded polysilicon, can obtain 0.18 required μ m live width figure on substrate, thereby obtain required 0.18 μ m live width figure by I Lithography machine through after corresponding steps, processing step is simple and convenient, utilize I Lithography glue to obtain 0.18 μ m live width figure, can applicable scientific research and development need, reduce development cost, safe and reliable.
Description of drawings
Fig. 1 forms the generalized section of 0.18 μ m photoresist after for the mask aligner photoetching that is 0.13 μ m of the existing 193nm of employing wavelength limit resolution.
Fig. 2 utilizes the photoresist in Fig. 1 to corrode rear generalized section.
Fig. 3 is that to adopt limiting resolution be generalized section after the I Lithography machine photoetching for the first time of 0.5 μ m in the present invention.
Fig. 4 is that the present invention utilizes the photoresist in Fig. 3 to corrode for the first time rear generalized section
Fig. 5 is rear generalized section after the I Lithography machine photoetching for the second time of 0.5 μ m for this aspect adopts limiting resolution.
Fig. 6 is that the present invention utilizes the photoresist in Fig. 5 to corrode for the second time rear generalized section.
Description of reference numerals: 1-substrate, 2-polysilicon, 3-photoresist and 4-shelter the location photoresist.
Embodiment
The invention will be further described below in conjunction with concrete drawings and Examples.
As Fig. 3～shown in Figure 6: obtain 0.18 μ m live width image in order to utilize I Lithography machine, photoetching method of the present invention comprises the steps:
A, photoetching for the first time: have at surface deposition to apply photoresist 3 on the substrate 1 of polysilicon 2, described photoresist 3 is covered in the surface of polysilicon 2; Utilize I Lithography machine to carry out photoetching to above-mentioned photoresist 3, keep the photoresist 3 of desired location; The material of substrate 1 comprises silicon;
As shown in Figure 3: by I Lithography machine, above-mentioned photoresist 3 is carried out photoetching, remove the photoresist 3 that does not need the position, keep simultaneously covering desired location photoresist 3, the width of described reservation photoresist 3 is about 10 μ m, much larger than 0.18 μ m;
B, corrosion for the first time: utilize the polysilicon 2 on the above-mentioned photoresist 3 above-mentioned substrates of erosion removal, and at the rear removal photoresist 3 of corrosion polysilicon 2;
As shown in Figure 4: adopt conventional etching process corrosion polysilicon 2, when the polysilicon 2 that photoresist 3 shield portions are arranged is not corroded, as the basis that forms 0.18 μ m live width figure; The rear removal photoresist 3 of corrosion polysilicon 2 is convenient to next step technological operation;
C, lithography registration for the second time: on substrate 1 corresponding to the surface-coated photoresist 3 after erosion removal polysilicon 2, and apply corresponding to the side surface that contacts with photoresist 3 at polysilicon 2 and shelter location photoresist 4, the described photoresist 3 of sheltering location photoresist 4 and polysilicon 2 one sides links into an integrated entity; By mask aligner alignment side-play amount is revised make shelter the location photoresist 4 width be 0.18 μ m;
As shown in Figure 5: because I Lithography facility have higher alignment precision, described alignment precision is greater than 0.18 μ m, according to keeping the vestige of photoresist 3 after photoetching for the first time, can can make the width of sheltering location photoresist 4 that rides on polysilicon 2 after polysilicon 2 is carved offset correction by I Lithography mantle is 0.18 μ m, simultaneously the substrate 1 surface-coated photoresist 3 after corrosion polysilicon 2;
D, corrosion for the second time: polycrystalline 2 silicon on the above-mentioned substrate 1 of erosion removal after photoetching, obtaining sheltering location photoresist 4 below width is the polysilicon graphics of 0.18 μ m;
As shown in Figure 6: when sheltering location photoresist 4 by what obtain 0.18 μ m live width after lithography registration for the second time, remove corresponding polysilicon 2 by conventional polysilicon etching process, thereby can obtain corresponding polysilicon 2 in desired location, the described width that obtains polysilicon 2 is consistent with the width of sheltering location photoresist 4, is 0.18 μ m.
the present invention first coordinates post-etching to obtain corresponding polysilicon 2 with photoresist 3 by I Lithography machine, then utilize I Lithography mantle offset correction at quarter to obtain being coated on sheltering on polysilicon 2 and locate photoresist 4, make the width of sheltering location photoresist 4 reach accurate 0.18 μ m, after utilization is sheltered location photoresist 4 pairs of polysilicons 2 and is corroded, can obtain 0.18 required μ m live width figure on substrate 1, thereby obtain required 0.18 μ m live width figure by I Lithography machine through after corresponding steps, processing step is simple and convenient, utilize I Lithography glue to obtain 0.18 μ m live width figure, can applicable scientific research and development need, reduce development cost, safe and reliable.
Claims (2)
1. an I Lithography machine is realized the method for 0.18 μ m live width figure with two inferior photoetching processes, and it is characterized in that: described photoetching method comprises the steps:
(a), photoetching for the first time: the upper photoresist (3) that applies of substrate (1) of polysilicon (2) is arranged at surface deposition, and described photoresist (3) is covered in the surface of polysilicon (2); Utilize I Lithography machine to carry out photoetching to above-mentioned photoresist (3), keep the photoresist (3) of desired location;
(b), corrosion for the first time: utilize the polysilicon (2) on the above-mentioned substrate of above-mentioned photoresist (3) erosion removal (1), and remove photoresist (3) after corrosion polysilicon (2);
(c), lithography registration for the second time: upper corresponding to the surface-coated photoresist (3) after erosion removal polysilicon (2) at substrate (1), and apply corresponding to the side surface that contacts with photoresist (3) at polysilicon (2) and shelter location photoresist (4), the described photoresist (3) of sheltering location photoresist (4) and polysilicon (2) one sides links into an integrated entity; Utilizing I Lithography mantle side-play amount at quarter to revise and making the width of sheltering location photoresist (4) is 0.18 μ m;
(d), corrosion for the second time: the polysilicon (2) after the upper photoetching of the above-mentioned substrate of erosion removal (1), obtaining sheltering location photoresist (4) below width is the polysilicon graphics of 0.18 μ m.
2. I Lithography machine according to claim 1 is realized the method for 0.18 μ m live width figure with two inferior photoetching processes, and it is characterized in that: the material of described substrate (1) comprises silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110386481 CN102403200B (en) | 2011-11-29 | 2011-11-29 | Method for realizing pattern with line width of 0.18[mu]m by double photoetching method for I line photoetching machine |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110386481 CN102403200B (en) | 2011-11-29 | 2011-11-29 | Method for realizing pattern with line width of 0.18[mu]m by double photoetching method for I line photoetching machine |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102403200A CN102403200A (en) | 2012-04-04 |
| CN102403200B true CN102403200B (en) | 2013-06-26 |
Family
ID=45885286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110386481 Active CN102403200B (en) | 2011-11-29 | 2011-11-29 | Method for realizing pattern with line width of 0.18[mu]m by double photoetching method for I line photoetching machine |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102403200B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106933064B (en) * | 2017-03-27 | 2018-11-09 | 上海华力微电子有限公司 | Realize the photoetching process of smaller line width |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01304457A (en) * | 1988-06-02 | 1989-12-08 | Fujitsu Ltd | Pattern forming method |
| JP2006049642A (en) * | 2004-08-05 | 2006-02-16 | Sumitomo Metal Mining Package Materials Co Ltd | Method of manufacturing double-sided interconnection tape carrier and tape carrier manufactured thereby |
| CN101201544B (en) * | 2006-12-11 | 2011-11-02 | 上海华虹Nec电子有限公司 | Semiconductor photolithography method |
| US7994060B2 (en) * | 2009-09-01 | 2011-08-09 | International Business Machines Corporation | Dual exposure track only pitch split process |
-
2011
- 2011-11-29 CN CN 201110386481 patent/CN102403200B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN102403200A (en) | 2012-04-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101295129B (en) | Optical short distance amending method | |
| TWI541588B (en) | Photomask for manufacturing device, and pattern transfer method | |
| KR101443531B1 (en) | Photo mask manufacturing method, photo mask, pattern transfer method and flat pannel display manufacturing method | |
| CN101349864A (en) | Photomask, manufacturing method thereof, and pattern transfer method | |
| CN102236247A (en) | Preparation method of photomask | |
| CN102122113A (en) | Photoetching method | |
| CN103034044A (en) | Multi-gray scale photomask, manufacturing method of multi-gray scale photomask and pattern transfer method | |
| CN101916039A (en) | Manufacturing method of mask plate | |
| CN102096308B (en) | Mask graph, method for manufacturing mask, and method for correcting mask graph | |
| CN111916425B (en) | Semiconductor Formation Method and Structure | |
| CN1837956B (en) | Gray mask and method for manufacturing thin film transistor substrate | |
| CN102403200B (en) | Method for realizing pattern with line width of 0.18[mu]m by double photoetching method for I line photoetching machine | |
| CN103345117B (en) | Mask and liquid crystal display manufacturing method | |
| KR101176262B1 (en) | Multi-gray scale photomask and pattern transfer method | |
| JP5644290B2 (en) | Photomask manufacturing method | |
| CN103021803A (en) | Method for protecting thick metal layer photoetching alignment mark | |
| CN108183123B (en) | Organic light emitting display panel and manufacturing method thereof | |
| TW200502677A (en) | Mask blank, mask blank manufacturing method, transfer mask manufacturing method, and semiconductor device manufacturing method | |
| CN103050383B (en) | A kind of method for eliminating side lobe pattern | |
| US9977324B2 (en) | Phase shift mask and method of forming patterns using the same | |
| CN111077728A (en) | Photomask and image calibration method | |
| TWI553705B (en) | Method for forming semiconductor structure without mask process | |
| CN102543748B (en) | Manufacturing method of semiconductor device | |
| US7939226B2 (en) | Binary mask, method for fabricating the binary mask, and method for fabricating fine pattern of semiconductor device using binary mask | |
| KR20100010696A (en) | Photomask having alignment pattern for inspecting photomask and method for fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |