CN1139110C - 在衬底中用于填充槽的方法 - Google Patents
在衬底中用于填充槽的方法 Download PDFInfo
- Publication number
- CN1139110C CN1139110C CNB971967237A CN97196723A CN1139110C CN 1139110 C CN1139110 C CN 1139110C CN B971967237 A CNB971967237 A CN B971967237A CN 97196723 A CN97196723 A CN 97196723A CN 1139110 C CN1139110 C CN 1139110C
- Authority
- CN
- China
- Prior art keywords
- groove
- substrate
- reference layer
- fill
- employed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
Landscapes
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
Abstract
Description
Claims (13)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19629766A DE19629766C2 (de) | 1996-07-23 | 1996-07-23 | Herstellverfahren von Shallow-Trench-Isolationsbereiche in einem Substrat |
| DE19629766.4 | 1996-07-23 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1226343A CN1226343A (zh) | 1999-08-18 |
| CN1139110C true CN1139110C (zh) | 2004-02-18 |
Family
ID=7800640
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB971967210A Expired - Fee Related CN1139109C (zh) | 1996-07-23 | 1997-07-22 | 在半导体衬底中建立高导电性埋入的侧面绝缘区域的方法 |
| CNB971967237A Expired - Fee Related CN1139110C (zh) | 1996-07-23 | 1997-07-22 | 在衬底中用于填充槽的方法 |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB971967210A Expired - Fee Related CN1139109C (zh) | 1996-07-23 | 1997-07-22 | 在半导体衬底中建立高导电性埋入的侧面绝缘区域的方法 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US6551902B1 (zh) |
| EP (2) | EP0914678B1 (zh) |
| JP (2) | JP2000515321A (zh) |
| KR (2) | KR100428700B1 (zh) |
| CN (2) | CN1139109C (zh) |
| AT (2) | ATE256340T1 (zh) |
| DE (3) | DE19629766C2 (zh) |
| WO (2) | WO1998003991A2 (zh) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU4059800A (en) * | 1999-04-02 | 2000-10-23 | Silicon Valley Group Thermal Systems, Llc | Improved trench isolation process to deposit a trench fill oxide prior to sidewall liner oxidation growth |
| DE10029288A1 (de) * | 2000-06-14 | 2002-01-03 | Infineon Technologies Ag | Verfahren zur Herstellung einer planaren Maske auf topologiehaltigen Oberflächen |
| US6541401B1 (en) * | 2000-07-31 | 2003-04-01 | Applied Materials, Inc. | Wafer pretreatment to decrease rate of silicon dioxide deposition on silicon nitride compared to silicon substrate |
| WO2005001939A1 (ja) * | 2003-06-30 | 2005-01-06 | Rohm Co., Ltd. | イメージセンサおよびフォトダイオードの分離構造の形成方法 |
| TWI353644B (en) * | 2007-04-25 | 2011-12-01 | Ind Tech Res Inst | Wafer level packaging structure |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4472240A (en) * | 1981-08-21 | 1984-09-18 | Tokyo Shibaura Denki Kabushiki Kaisha | Method for manufacturing semiconductor device |
| JPS59124141A (ja) * | 1982-12-28 | 1984-07-18 | Toshiba Corp | 半導体装置の製造方法 |
| KR950002948B1 (ko) * | 1991-10-10 | 1995-03-28 | 삼성전자 주식회사 | 반도체 장치의 금속층간 절연막 형성방법 |
| DE69232648T2 (de) * | 1991-11-29 | 2003-02-06 | Sony Corp., Tokio/Tokyo | Verfahren zur Herstellung einer Grabenisolation mittels eines Polierschritts und Herstellungsverfahren für eine Halbleitervorrichtung |
| JP2812599B2 (ja) * | 1992-02-06 | 1998-10-22 | シャープ株式会社 | 半導体装置の製造方法 |
| DE4211050C2 (de) * | 1992-04-02 | 1995-10-19 | Siemens Ag | Verfahren zur Herstellung eines Bipolartransistors in einem Substrat |
| EP0582724A1 (de) * | 1992-08-04 | 1994-02-16 | Siemens Aktiengesellschaft | Verfahren zur lokal und global planarisierenden CVD-Abscheidung von SiO2-Schichten auf strukturierten Siliziumsubstraten |
| JP2705513B2 (ja) * | 1993-06-08 | 1998-01-28 | 日本電気株式会社 | 半導体集積回路装置の製造方法 |
| JPH07106412A (ja) * | 1993-10-07 | 1995-04-21 | Toshiba Corp | 半導体装置およびその製造方法 |
| US5536675A (en) * | 1993-12-30 | 1996-07-16 | Intel Corporation | Isolation structure formation for semiconductor circuit fabrication |
| KR960002714A (ko) * | 1994-06-13 | 1996-01-26 | 김주용 | 반도체소자의 소자분리절연막 형성방법 |
| US5872043A (en) * | 1996-07-25 | 1999-02-16 | Industrial Technology Research Institute | Method of planarizing wafers with shallow trench isolation |
-
1996
- 1996-07-23 DE DE19629766A patent/DE19629766C2/de not_active Expired - Fee Related
-
1997
- 1997-07-22 AT AT97935454T patent/ATE256340T1/de not_active IP Right Cessation
- 1997-07-22 CN CNB971967210A patent/CN1139109C/zh not_active Expired - Fee Related
- 1997-07-22 JP JP10506460A patent/JP2000515321A/ja active Pending
- 1997-07-22 WO PCT/DE1997/001542 patent/WO1998003991A2/de not_active Ceased
- 1997-07-22 CN CNB971967237A patent/CN1139110C/zh not_active Expired - Fee Related
- 1997-07-22 DE DE59711114T patent/DE59711114D1/de not_active Expired - Fee Related
- 1997-07-22 EP EP97935455A patent/EP0914678B1/de not_active Expired - Lifetime
- 1997-07-22 AT AT97935455T patent/ATE282247T1/de not_active IP Right Cessation
- 1997-07-22 JP JP10506459A patent/JP2000515320A/ja not_active Abandoned
- 1997-07-22 KR KR10-1999-7000411A patent/KR100428700B1/ko not_active Expired - Fee Related
- 1997-07-22 KR KR10-1999-7000437A patent/KR100427856B1/ko not_active Expired - Fee Related
- 1997-07-22 DE DE59712073T patent/DE59712073D1/de not_active Expired - Lifetime
- 1997-07-22 EP EP97935454A patent/EP0928500B1/de not_active Expired - Lifetime
- 1997-07-22 WO PCT/DE1997/001543 patent/WO1998003992A1/de not_active Ceased
-
1999
- 1999-01-25 US US09/237,174 patent/US6551902B1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000515321A (ja) | 2000-11-14 |
| ATE256340T1 (de) | 2003-12-15 |
| DE19629766C2 (de) | 2002-06-27 |
| DE19629766A1 (de) | 1998-01-29 |
| EP0914678A1 (de) | 1999-05-12 |
| EP0914678B1 (de) | 2004-11-10 |
| WO1998003991A3 (de) | 1998-03-26 |
| CN1226342A (zh) | 1999-08-18 |
| KR100428700B1 (ko) | 2004-04-30 |
| DE59712073D1 (de) | 2004-12-16 |
| KR20000067947A (ko) | 2000-11-25 |
| KR20000067936A (ko) | 2000-11-25 |
| DE59711114D1 (de) | 2004-01-22 |
| CN1226343A (zh) | 1999-08-18 |
| EP0928500B1 (de) | 2003-12-10 |
| ATE282247T1 (de) | 2004-11-15 |
| WO1998003992A1 (de) | 1998-01-29 |
| JP2000515320A (ja) | 2000-11-14 |
| CN1139109C (zh) | 2004-02-18 |
| KR100427856B1 (ko) | 2004-04-30 |
| US6551902B1 (en) | 2003-04-22 |
| WO1998003991A2 (de) | 1998-01-29 |
| EP0928500A2 (de) | 1999-07-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: INFINEON TECHNOLOGIES AG Free format text: FORMER OWNER: SIEMENS AG Effective date: 20120222 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20120222 Address after: Federal Republic of Germany City, Laura Ibiza Berger Patentee after: Infineon Technologies AG Address before: Munich, Germany Patentee before: Siemens AG |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040218 Termination date: 20160722 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |