DE3684591D1 - Halbleiteranordnung mit flachem uebergang mit autopassiviertem rand. - Google Patents

Halbleiteranordnung mit flachem uebergang mit autopassiviertem rand.

Info

Publication number
DE3684591D1
DE3684591D1 DE8686117144T DE3684591T DE3684591D1 DE 3684591 D1 DE3684591 D1 DE 3684591D1 DE 8686117144 T DE8686117144 T DE 8686117144T DE 3684591 T DE3684591 T DE 3684591T DE 3684591 D1 DE3684591 D1 DE 3684591D1
Authority
DE
Germany
Prior art keywords
autopassivated
edge
semiconductor arrangement
flat transition
transition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686117144T
Other languages
English (en)
Inventor
Luciano Gandolfi
Salvatore Dr Musumeci
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Microelettronica SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Microelettronica SpA filed Critical SGS Microelettronica SpA
Application granted granted Critical
Publication of DE3684591D1 publication Critical patent/DE3684591D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/40—Vertical BJTs
    • H10D10/441—Vertical BJTs having an emitter-base junction ending at a main surface of the body and a base-collector junction ending at a lateral surface of the body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137—Collector regions of BJTs
DE8686117144T 1985-12-11 1986-12-09 Halbleiteranordnung mit flachem uebergang mit autopassiviertem rand. Expired - Fee Related DE3684591D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT06628/85A IT1202311B (it) 1985-12-11 1985-12-11 Dispositivo a semiconduttore con una giunzione piana a terminazione auto passivante

Publications (1)

Publication Number Publication Date
DE3684591D1 true DE3684591D1 (de) 1992-04-30

Family

ID=11121599

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686117144T Expired - Fee Related DE3684591D1 (de) 1985-12-11 1986-12-09 Halbleiteranordnung mit flachem uebergang mit autopassiviertem rand.

Country Status (5)

Country Link
US (1) US4805004A (de)
EP (1) EP0232510B1 (de)
JP (1) JPS62189754A (de)
DE (1) DE3684591D1 (de)
IT (1) IT1202311B (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1214805B (it) * 1984-08-21 1990-01-18 Ates Componenti Elettron Spositivi a semiconduttore con giunprocesso per la fabbricazione di dizioni planari a concentrazione di carica variabile e ad altissima tensione di breakdown
US5223919A (en) * 1987-02-25 1993-06-29 U. S. Philips Corp. Photosensitive device suitable for high voltage operation
EP0311816A1 (de) * 1987-10-15 1989-04-19 BBC Brown Boveri AG Halbleiterbauelement und Verfahren zu dessen Herstellung
EP0360036B1 (de) * 1988-09-20 1994-06-01 Siemens Aktiengesellschaft Planarer pn-Übergang hoher Spannungsfestigkeit
FR2650122B1 (fr) * 1989-07-21 1991-11-08 Motorola Semiconducteurs Dispositif semi-conducteur a haute tension et son procede de fabrication
JP2523896Y2 (ja) * 1989-11-08 1997-01-29 能美防災株式会社 防水型火災感知器及びそのパッキン
US5124271A (en) * 1990-06-20 1992-06-23 Texas Instruments Incorporated Process for fabricating a BiCMOS integrated circuit
DE4119904A1 (de) * 1991-06-17 1992-12-24 Telefunken Electronic Gmbh Halbleiteranordnung
DE69324119T2 (de) * 1992-12-21 1999-08-05 Stmicroelectronics, Inc., Carrollton, Tex. Diodenstruktur mit PN-Übergang
EP0632502B1 (de) * 1993-06-28 1999-03-17 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Bipolar-Leistungstransistor mit hoher Kollektor-Durchbrucksspannung und Verfahren zu seiner Herstellung
EP0974165B1 (de) * 1998-02-09 2009-03-25 Nxp B.V. Halbleiteranordnung mit einem bipolartransistor und verfahren zur herstellung
GB9804177D0 (en) * 1998-02-28 1998-04-22 Philips Electronics Nv Semiconductor switch devices and their manufacture
JP4736180B2 (ja) * 2000-11-29 2011-07-27 株式会社デンソー 半導体装置およびその製造方法
FR2828767B1 (fr) * 2001-08-14 2003-12-12 Thales Sa Transistor bipolaire a tension de claquage elevee
US7560787B2 (en) * 2005-12-22 2009-07-14 Fairchild Semiconductor Corporation Trench field plate termination for power devices
DE102006055885B4 (de) 2006-11-27 2018-02-15 Infineon Technologies Austria Ag Verfahren zum Dotieren eines Halbleiterkörpers
DE102007001108B4 (de) * 2007-01-04 2012-03-22 Infineon Technologies Ag Diode und Verfahren zu ihrer Herstellung
US7800196B2 (en) * 2008-09-30 2010-09-21 Northrop Grumman Systems Corporation Semiconductor structure with an electric field stop layer for improved edge termination capability
US8872278B2 (en) 2011-10-25 2014-10-28 Fairchild Semiconductor Corporation Integrated gate runner and field implant termination for trench devices
EP4333069A1 (de) * 2022-08-31 2024-03-06 Nexperia B.V. Vertikale halbleitervorrichtung und herstellungsverfahren dafür

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2173729B1 (de) * 1972-02-29 1977-07-15 Radiotechnique Compelec
JPS50137478A (de) * 1974-04-18 1975-10-31
US4165516A (en) * 1975-04-28 1979-08-21 U.S. Philips Corporation Semiconductor device and method of manufacturing same
JPS5230176A (en) * 1975-09-02 1977-03-07 Matsushita Electronics Corp Manufacturing system of npn-transistor
JPS5356972A (en) * 1976-11-01 1978-05-23 Mitsubishi Electric Corp Mesa type semiconductor device
US4374389A (en) * 1978-06-06 1983-02-15 General Electric Company High breakdown voltage semiconductor device
GB2134705B (en) * 1983-01-28 1985-12-24 Philips Electronic Associated Semiconductor devices
FR2557367B1 (fr) * 1983-12-23 1986-12-05 Thomson Csf Structure semiconductrice a tenue en tension elevee avec sillon peripherique implante et son procede de fabrication
US4605948A (en) * 1984-08-02 1986-08-12 Rca Corporation Semiconductor structure for electric field distribution

Also Published As

Publication number Publication date
US4805004A (en) 1989-02-14
EP0232510A3 (en) 1988-01-20
EP0232510A2 (de) 1987-08-19
IT8506628A0 (it) 1985-12-11
IT1202311B (it) 1989-02-02
JPS62189754A (ja) 1987-08-19
EP0232510B1 (de) 1992-03-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee