EE200200261A - Meetod räninanostruktuuri, ränikvantviikude massiivi ning sellel baseeruvate komponentide formeerimiseks - Google Patents

Meetod räninanostruktuuri, ränikvantviikude massiivi ning sellel baseeruvate komponentide formeerimiseks

Info

Publication number
EE200200261A
EE200200261A EEP200200261A EEP200200261A EE200200261A EE 200200261 A EE200200261 A EE 200200261A EE P200200261 A EEP200200261 A EE P200200261A EE P200200261 A EEP200200261 A EE P200200261A EE 200200261 A EE200200261 A EE 200200261A
Authority
EE
Estonia
Prior art keywords
silicon
array
forming
components based
nanostructure
Prior art date
Application number
EEP200200261A
Other languages
English (en)
Estonian (et)
Inventor
K. Smirnov Valery
S. Kibalov Dmitri
Original Assignee
Sceptre Electronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sceptre Electronics Limited filed Critical Sceptre Electronics Limited
Publication of EE200200261A publication Critical patent/EE200200261A/xx

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/014Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/812Single quantum well structures
    • H10D62/813Quantum wire structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Physical Vapour Deposition (AREA)
  • Thin Film Transistor (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Drying Of Semiconductors (AREA)
EEP200200261A 1999-11-25 2000-10-02 Meetod räninanostruktuuri, ränikvantviikude massiivi ning sellel baseeruvate komponentide formeerimiseks EE200200261A (et)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
RU99124768/28A RU2173003C2 (ru) 1999-11-25 1999-11-25 Способ образования кремниевой наноструктуры, решетки кремниевых квантовых проводков и основанных на них устройств
PCT/IB2000/001397 WO2001039259A1 (en) 1999-11-25 2000-10-02 Methods of formation of a silicon nanostructure, a silicon quantum wire array and devices based thereon

Publications (1)

Publication Number Publication Date
EE200200261A true EE200200261A (et) 2003-08-15

Family

ID=20227346

Family Applications (1)

Application Number Title Priority Date Filing Date
EEP200200261A EE200200261A (et) 1999-11-25 2000-10-02 Meetod räninanostruktuuri, ränikvantviikude massiivi ning sellel baseeruvate komponentide formeerimiseks

Country Status (23)

Country Link
US (1) US6274007B1 (is)
EP (1) EP1104011A1 (is)
JP (1) JP2001156050A (is)
KR (1) KR20020069195A (is)
CN (1) CN1399791A (is)
AU (1) AU7547400A (is)
BG (1) BG106739A (is)
BR (1) BR0016095A (is)
CA (1) CA2392307A1 (is)
CZ (1) CZ20021824A3 (is)
EE (1) EE200200261A (is)
HR (1) HRP20020459A2 (is)
HU (1) HUP0203517A2 (is)
IL (1) IL149832A0 (is)
IS (1) IS6393A (is)
MX (1) MXPA02005281A (is)
NO (1) NO20022427L (is)
PL (1) PL355890A1 (is)
RU (1) RU2173003C2 (is)
SK (1) SK7442002A3 (is)
WO (1) WO2001039259A1 (is)
YU (1) YU38202A (is)
ZA (1) ZA200204822B (is)

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Also Published As

Publication number Publication date
WO2001039259A1 (en) 2001-05-31
AU7547400A (en) 2001-06-04
PL355890A1 (pl) 2004-05-31
ZA200204822B (en) 2003-11-26
EP1104011A1 (en) 2001-05-30
YU38202A (sh) 2006-08-17
IS6393A (is) 2002-05-24
CA2392307A1 (en) 2001-05-31
CN1399791A (zh) 2003-02-26
US6274007B1 (en) 2001-08-14
SK7442002A3 (en) 2003-05-02
NO20022427D0 (no) 2002-05-22
CZ20021824A3 (cs) 2004-10-13
HRP20020459A2 (en) 2005-10-31
BG106739A (bg) 2003-08-29
IL149832A0 (en) 2002-11-10
BR0016095A (pt) 2004-03-23
MXPA02005281A (es) 2006-02-10
HUP0203517A2 (en) 2003-07-28
NO20022427L (no) 2002-06-25
JP2001156050A (ja) 2001-06-08
KR20020069195A (ko) 2002-08-29
RU2173003C2 (ru) 2001-08-27

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