Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/117—Shapes of semiconductor bodies
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
  • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
  • H10D84/221—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only diodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations

Definitions

• the invention relates to a semiconductor device consisting of diodes connected in parallel with a parallel to the method for producing such a semiconductor arrangement.
• Anti-parallel circuits of diodes are used in control and regulating circuits, for example in DC converters. They can consist of discrete individual elements and can be combined and connected to form a structural unit on a carrier body.
• spatially separated layer sequences can also be arranged in an integrated manner as diode structures in a semiconductor body and interconnected in an anti-parallel manner using conductor tracks.
• a disadvantage of the combination of discrete components is the special effort for the completion of the individual elements and for their assembly and interconnection souie the often undesirably high space requirements and the resulting restrictions in use.
• the disadvantages of the integrated arrangement with regard to the low electrical requirements for such circuits are the high process complexity for special diffusion and flasking steps.
• the object of the invention is to determine an anti-parallel connection of diodes with the most favorable combination of their individual elements in terms of construction and manufacture.
• the solution to this problem in a semiconductor arrangement of the type mentioned at the outset is that it comprises a semiconductor body with a base region made up of a zone of one conductivity type and with a further region adjacent to each side of the base region, which forms a pn junction with it and corresponds to it Zone of the other side of the base region has a staggered zone of smaller surface area for each one with respect to the other spatially and electrically antiparal diode structure as well as with contact metal coatings for the electrical connection of the two dipden structures.
• the solution to the problem further consists in a method for producing such a semiconductor arrangement, in which, in a semiconductor output wafer of one conductivity type between the main surfaces, a layer sequence from a central zone and from two additional zones, each with an intermediate pn-, by diffusion of doping material of the other conductivity type on both sides. Transition is formed in which, after masking with a pattern, the starting disk is provided on both sides with a structure of trench-shaped depressions which are parallel to one another and each arranged on a gap opposite one another and which interrupt the nearest pn transition, in each case a coating of at least one contact metal is applied to the starting disk, and in which the disk is at least along all of the depressions in semiconductor components of smaller surface area, each with anti parallel diode structures is divided.
• the depressions can be created by etching or by ultrasonic drilling or by sawing.
• the thin, highly doped layer of the same conductivity type provided in the surface sections of the base region exposed by the depressions can be produced by diffusion or by vapor deposition and alloying of doping metals.
• the contact metal coatings can be produced by electroless deposition of contact metals or by vapor deposition and alloying.
• the surfaces of the starting disc can be roughened by sandblasting.
• contact metals are used which form an ohmic contact with the semiconductor material of the starting disk, and that the thin, highly doped layer and the contact metal coatings are produced in one process step.
• the advantage of the invention is that a compact arrangement of an anti-parallel connection of two diodes that meets all technical requirements can be achieved with a minimum of well-known method steps.
• FIGS. 1 and 2 show in cross section the structure of the Semiconductor arrangement according to the invention
• FIG. 2 shows in perspective a semiconductor output disk, from which semiconductor arrangements are manufactured in the manner according to the invention. The same designations are used for the same parts in all figures.
• the semiconductor body according to FIG. 1 consists of an np structure I corresponding to a first diode and of the identical structure II, which is spatially oppositely oriented and arranged offset in the zone plane, corresponding to a forward, anti-parallel diode. Both structures have essentially the same surface area and the same thickness.
• both structures is a central, n-conducting base region 1, on one side of which the p-conducting zone 2 adjoins the pn junction J1 formed thereby and thereby forms the structure I, and on the other side spatially adjoining the structure I.
• the p-type zone 3 adjoins the pn junction 32 formed thereby and thereby forms the structure II.
• the pn junction 31 of structure I appears on both end surfaces of zone 2 and the pn junction 32 on both end surfaces of zone 3.
• the thickness of the zones of both structures I and II and their surface area are essentially determined by the requirements for their physical and electrical properties during use.
• the structures are only stressed in the forward direction, so that special measures for surface stabilization and for improving the blocking ability are not required.
• transition from one structure to the other i.e. the shape of the edge surface of the further zones 2, 3 is not critical and, in accordance with the production methods provided for forming the base region of each structure, is essentially perpendicular to the zone plane of the arrangement.
• the latter is in each case provided with a highly doped, thin surface layer 4 or 5 of the same conductivity type.
• n + conductive In the illustrated off the corresponding sections are n + conductive.
• Both surfaces of the semiconductor body which run in the same stepped manner furthermore each have a contact metal coating 6 or 7, which can also be formed from partial layers.
• Aluminum, silver, nickel, for example, are considered as contact metals.
• contact metals can be used which are suitable for forming an ohmic contact with the semiconductor material, e.g. Aluminum or a combination of gold and antimony. This makes it possible to produce the thin, highly doped layer 4 or 5 and the contact metal coating 6 or 7 in one process step.
• the semiconductor material e.g. Aluminum or a combination of gold and antimony.
• the semiconductor arrangement according to the invention is surprisingly simple, alternating from a layer sequence with three layer-shaped zones of opposite conductivity type, e.g. a pnp structure is possible, and that production from a larger starting body by cutting along marking lines m .. is particularly advantageous.
• a large-area semiconductor wafer of a first conductivity type is advantageously assumed.
• a pnp layer sequence 1, 2, 3 is produced by known, mutual diffusion of impurities of the other conduction type, for example a boron diffusion at temperatures above 1200 ° C. into an n-type output disk.
• the output disk is provided on both sides with depressions 10 and 20 in accordance with a pattern predetermined by the surface expansion and surface shape of the semiconductor components provided.
• the output disk is, for example, appropriately masked on both sides and subjected to an etching process in which trench-shaped depressions 10 and 20, which run parallel to each other, are arranged on a gap with respect to those on the other side and interrupt the adjacent pn junction, which as a result form an approximately meandering cross section of the disk.
• etching solutions are used for the etching treatment of the starting disk.
• the depressions 10, 20 can advantageously also be produced by ultrasonic drilling or by sawing.
• a thin, highly doped surface layer 4, 5 with a thickness of up to approximately 20 ⁇ m with the conductivity type of the base region 1 is produced in the bottom surface thereof.
• This can be done by known diffusion, for example of phosphorus or boron.
• the surface layer 4, 5 can also be produced by vapor deposition and alloying of a contact metal with doping property, for example aluminum or gold-antimony, in a manner known per se, as a result of which, in terms of process technology, the contact metal coatings 6, 7, ie the contact electrodes of the semiconductor body, are obtained at the same time .
• these coatings 6, 7 are produced by electroless deposition of contact metals, for example nickel, their adhesion to the semiconductor surface can be improved by sandblasting.
• the disk is divided along the marking lines m 1 , m 2 into components with a smaller surface area, as is particularly indicated in FIG. 2. This can advantageously be done using the laser technology.

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• Electrodes Of Semiconductors (AREA)
• Footwear And Its Accessory, Manufacturing Method And Apparatuses (AREA)

Applications Claiming Priority (2)

Publications (1)

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• 1978
  • 1978-12-23 DE DE2855972A patent/DE2855972C2/de not_active Expired
• 1979
  • 1979-12-11 GB GB8101369A patent/GB2064869B/en not_active Expired
  • 1979-12-11 JP JP50005679A patent/JPS55501161A/ja active Pending
  • 1979-12-11 WO PCT/DE1979/000145 patent/WO1980001334A1/de not_active Ceased
  • 1979-12-11 US US06/503,078 patent/US4525924A/en not_active Expired - Fee Related
  • 1979-12-19 IT IT28210/79A patent/IT1126607B/it active
• 1980
  • 1980-07-01 EP EP80900001A patent/EP0020666A1/de not_active Withdrawn
  • 1980-12-17 SE SE8008879A patent/SE443476B/sv not_active IP Right Cessation

Non-Patent Citations (1)

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