EP0051693B1 - Mémoire morte électriquement commutable - Google Patents

Mémoire morte électriquement commutable Download PDF

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Publication number
EP0051693B1
EP0051693B1 EP80106964A EP80106964A EP0051693B1 EP 0051693 B1 EP0051693 B1 EP 0051693B1 EP 80106964 A EP80106964 A EP 80106964A EP 80106964 A EP80106964 A EP 80106964A EP 0051693 B1 EP0051693 B1 EP 0051693B1
Authority
EP
European Patent Office
Prior art keywords
storage
electrically switchable
gate sections
fet
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP80106964A
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German (de)
English (en)
Other versions
EP0051693A1 (fr
Inventor
Volkmar Götze
Ekkehard Dr. Miersch
Günther Potz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IBM Deutschland GmbH
International Business Machines Corp
Original Assignee
IBM Deutschland GmbH
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by IBM Deutschland GmbH, International Business Machines Corp filed Critical IBM Deutschland GmbH
Priority to DE8080106964T priority Critical patent/DE3070786D1/de
Priority to EP80106964A priority patent/EP0051693B1/fr
Priority to JP56128251A priority patent/JPS5837637B2/ja
Priority to US06/317,669 priority patent/US4445202A/en
Publication of EP0051693A1 publication Critical patent/EP0051693A1/fr
Application granted granted Critical
Publication of EP0051693B1 publication Critical patent/EP0051693B1/fr
Expired legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17712—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays one of the matrices at least being reprogrammable

Definitions

  • the invention relates to electrically switchable read-only memories of the type specified in the preamble of patent claim 1.
  • Such read-only memories are used to an increasing extent in computer technology in order to keep fixed data permanently, ie. H. to store non-volatile.
  • a variety of forms of such read-only memories are known both from a technological point of view and with regard to their classification in the overall design of the respective computer structure.
  • PLAs Programmable Logic Arrays
  • PLAs composed of ROMs (AND / OR fields) allow the direct implementation of (minimized) combinatorial logic in regular matrix arrangements.
  • ROMs such as PLAs, used as one-sided allocators offer various advantages, which make them increasingly attractive as a replacement for combinatorial logic, as a memory for tables, constants and programs, for code generation and conversion, than hard-wired multipliers and more.
  • memories have also already been described in connection with the construction of electrically changeable permanent memories, the cells of which each consist of an MNOS transistor or a transistor with a “floating” gate in series, each with an associated isolating transistor of the normal MOS type, cf. DE-OS 2 844 955 and DE-OS 2 937 337.
  • Fast switching between several functions is therefore no more possible than with the above-mentioned memories with electrical reprogramming option, to which group these memories also belong. They are only mentioned here with a view to a certain similarity of the respective semiconductor training.
  • the invention solves the problem of specifying a further improvement of such permanent memories, as can be used for PLAs, in the sense of higher functional densities, which in particular allow fast electrical switching between different functions and no high reprogramming voltages or special components require.
  • a PLA that can be personalized in two ways is selected as an example to explain the invention.
  • the PLA should offer two functional states F1 and F2 with different logic functions X and Y of inputs A, B, C and D, between which a fast electrical switchover should be possible.
  • the links should, for example, be as follows:
  • FIGS. 1 and 2 illustrate the associated personalization of two PLAs that can be personalized in a customary manner. Markings at the relevant matrix crossing points indicate whether one of the inputs A, B, C, D is included in the link.
  • 3 shows the summarized representation of both personalizations in a single PLA, which is intended to allow switching between the functional states F1 and F2, in accordance with the aim pursued by the present invention. Which of the two functional states F1, F2 is selected depends on the potential state (log. “0” or “1”) of a correspondingly provided pair of control lines c and c. This will be discussed in more detail in the later description of the exemplary embodiment.
  • Figs. 1 to 3 finally indicate the reference numerals 1 and 2, each consisting of a ROM matrix, AND field 1 and OR field 2, from which PLAs are known to be composed.
  • the personalization pattern shown schematically in FIG. 3 thus summarizes the functions shown in FIGS. 1 and 2. It can be understood as a superimposition of the individual personalization patterns for F1 (FIG. 1) and F2 (FIG. 2).
  • Such a PLA can now be designed to be very space-saving.
  • the new, highly-degradable coupling elements with their personalization options make it possible to implement PLAs with at least two independently selectable, permanently stamped linking functions using one and the same periphery with almost the amount of space that was previously required for only one function. This opens up a whole range of new areas of application for such permanent storage in a system context.
  • the coupling elements and their “wiring” must allow at least four different personalization options.
  • the coupling element between the input line for A and the product term line or line labeled L1 that is to say at the intersection A / L1
  • the coupling element at C / L1 effects a corresponding connection only in functional state F1 and the coupling element at A / L2 only in functional state F2.
  • no connection is provided at the intersection B / L2; input B is thus ignored with regard to the so-called product term formation on line L2.
  • Such a possible personalization state is usually referred to as a “don't care” position in a PLA.
  • FIG. 4 shows an exemplary embodiment of the invention with which the PLA functions marked in FIG. 3 are implemented.
  • Characteristic of the invention is the type of coupling elements or cells and the personalization states that can be carried out with these coupling elements, which were discussed above.
  • the coupling elements are designed as FETs, for which at least two gate sections are provided next to one another. In order for the associated switching path of such a coupling element to become conductive, it is necessary that the associated switch-on potentials are present on all of the two gate sections in the present example.
  • the at least two switchable logic functions F1 and F2 are structurally impressed in such a way that, in the case of a connection to be established only as part of one of the two functions, one of the gate sections with the control line relevant for this function selection and the remaining gate section of such a coupling element with the relevant input line is connected. Should be in the context of both functions on the relevant If a connection becomes effective at the intersection, both gate sections and thus the complete gate are connected together to the relevant input line. A "don't care" position is realized by not or not completely forming the coupling element in question, so that a connection cannot be effective at this point of intersection at any time.
  • the PLA which can be personalized twice as an exemplary embodiment, is described in more detail below.
  • the AND field labeled 1 with the inputs A, B, C and D and the OR field labeled 2 with the outputs X and Y can be seen.
  • the connection between the fields 1 and 2 becomes Manufactured via the (product term) lines L1, L2 and via the control lines c, c for determining the respective functional state F1 or F2.
  • N-channel enhancement-type MOSFETs are assumed for the exemplary embodiment. Their basic operating characteristics can be assumed to be known.
  • the illustration given in FIG. 4 is also limited to the peripheral circuit parts necessary for understanding the logic operation, such as. B.
  • the operating voltage supply via + V and the resistors labeled R The various drive circuits or generally peripheral circuits, such as input buffers, decoders, phase splitters, drivers etc., are not shown because the invention does not relate to them and the peripheral circuits can be implemented conventionally. In this regard, reference is made to the prior art literature mentioned at the beginning.
  • the z. B. to be provided exclusively in the functional state F1 at the intersection C / L1 in the AND field 1 is formed by the FET 3 with the two gate sections 4 and 5.
  • the gate section 4 is connected to the input C and the gate section 5 is connected to the control line c.
  • the FET 3 thus only becomes conductive if both the associated input C and the control line c have the logic “1” state. According to the agreement, this is only the case in functional state F1.
  • FIG. 4 An example of a "don't care" position in which the relevant input is ignored for both functional states F1 and F2 is the crossing point B / L2.
  • an FET 11 without gate (s) is shown in FIG. 4. Since field-effect transistors of the enhancement type, which are normally non-conductive, have been assumed in the exemplary embodiment, a conductive connection is never established at this crossing point. Of course, this personalization state can also be developed alternatively by not fulfilling one (or more) other prerequisites for an operational FET.
  • OR field 2 For the four crossing points provided in OR field 2, coupling elements of the same type are provided for personalization according to the same "wiring rules" as in the AND field 1 just discussed.
  • the output lines of the AND field designated L1, L2 are 1 to be regarded as input lines.
  • the output lines of OR field 2 are formed by the column lines for the (sum) terms X and Y.
  • L1 and L2 now represent input lines for the OR field denoted by 2.
  • the FET 15, 16 and 17 are ready for the leading state if the associated ones Input lines L1, L2 have the upper level (»1«).
  • the output line X already assumes the upper level (+ V) or the "1" state when L1 or L2 is positive (OR function). From this follows the logical equation: Is z. B. L1 positive, the X line connected to ground via R is raised via the conductive FET 15 in the direction of the operating voltage + V. The same applies to positive potential on the L2 line as a result of the then conductive FET 16.
  • PLAs with permanently impressed multiple personalization can be made available, which offer an extraordinarily fast switchover between the respective impressed functions by simply switching over control line potentials (c, c). It can also be seen that this multiple personalization does not have to be bought with a correspondingly multiple expenditure of additional coupling elements and thus with integrated training aimed at semiconductor surface.
  • FIGS. 5 and 6 show a top view and a cross-sectional view of a section of a PLA, which in the circuit diagram of FIG. 4 shows the four intersections with the coupling elements (FET) 12, 3, 11 and 19 and the inputs B and C includes.
  • FET coupling elements
  • FIGS. 5 and 6 are only schematic representations and are in no way to scale layouts.
  • a semiconductor substrate designated P su8 e.g. B. from silicon
  • doping strips N1, N2 and N3 are provided in the usual manner for MOSFET technology source and drain zones as doping strips N1, N2 and N3.
  • the connection to the operating voltage + V is indicated schematically via a load resistor R each.
  • the N1 and N2 doping strips on the other side form the (product term) lines L1 and L2.
  • N2 serves as a common source for the coupling elements of adjacent lines and is connected to ground, for example. Since two gate sections are provided for each coupling element in the selected embodiment, channel-supporting doping regions, e.g. B. N12 and N23 indicated.
  • polysilicon Two layers of (conductive) polycrystalline silicon, hereinafter referred to as polysilicon and referred to in the drawings as POLY 1 and POLY 2, and a metallization level, e.g. B. made of aluminum.
  • a metallization level e.g. B. made of aluminum.
  • the first layer of polysilicon POLY 1, depending on the desired cell state of the coupling element in question, only one of the two gate sections, for. B. 4 at FET 3, or a complete gate, such as. B. in the FET 12 with 2 connected gate halves 20, 21.
  • POLY 2 With the second layer of polysilicon, POLY 2, the c and c control lines as well as the gate half (s) to be connected to it, e.g. B. 5 and 22.
  • the input lines are arranged as metallization strips across the doping strips for N1, N2, N3 and the control lines c, c (POLY 2) above them. This is shown in FIGS. 5 and 6 for inputs B and C. It can be seen that the input B is connected to both gate sections 20, 21 via the contact points designated 23, 24 in the area of the FET 12. For input C it is apparent from FIG. 5 and even better from the cross section of FIG. 6 that the associated conductor line 25 with the gate section 4 of the FET 3 via the contact 26 and with the gate section 27 of the FET 19 the contact 28 is connected.
  • the invention can equally advantageously be used in the field of normal read-only memory (ROM), which can be regarded as components of PLAs, as explained at the beginning has been.
  • ROM read-only memory
  • the invention is fundamentally not limited to double memories which can be personalized. It can be seen, for example, that a three-fold personalization option can be achieved by providing three gate sections for the FET used as coupling elements.
  • the invention is not limited to the FET types on which the exemplary embodiments are based, but instead, taking into account the operating voltage and signal polarities to be selected accordingly, z. B. P-channel FET can be used.
  • the concept on which the invention is based is also not necessarily linked to FET technology. It can also be implemented in other types of technology today, e.g. B. in bipolar, Josephson, GaAs technology, etc. The same applies to the agreement of a differently chosen assignment of the potentials relative to the logical states and with respect to the materials used in the embodiment, z. As silicon, polysilicon and aluminum, for which there are many alternatives in the field of known semiconductor technology.

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Claims (10)

1. Mémoire morte électriquement commutable comportant des éléments de couplage qui conditionnent, selon l'état fonctionnel individuel qui leur est respectivement attribué, une connexion électriquement conductrice aux jonctions dans une matrice, caractérisé en ce que lesdits éléments de couplage (3, 6, 7, 9, 11 à 13, 15 à 19) sont des transistors à effet de champ comportant au moins deux parties de porte montées de façon contigue, où le chemin de connexion Source-Drain correspondant ne passe à l'état conducteur que lorsque toutes les parties de porte reçoivent les tensions appropriées, en ce que des tensions sont appliquées au moins aux deux fonctions commutables (F1, F2) de manière à ce que, et ceci dans le cas où une connexion doit être établie dans une desdites fonctions seulement (par exemple F1 ou F2), und des parties de porte (par exemple la partie 5 ou 22) soit connectée avec la ligne de commande (c ou c) correspondant à la sélection de la fonction et l'autre partie de porte (par exemple 4, 27) ou les autres parties de porte d'un élément de couplage de ce type (par exemple 3, 19) soit (ent) connectée (s) avec la ligne d'entrée (25) correspondant et, en ce que, dans le cas où des connexions sont à établir dans au moins les deux dites fonction (F1 et F2), les parties de porte respectives (par exemple 10) soient connectées en commun avec la ligne d'entrée correspondante (par exemple A).
2. Mémoire morte électriquement commutable selon la revendication 1, caractérisé en ce que plusieurs champs de mémoire de ce type (1, 2) sont assemblées pour former des réseaux logiques programmables (figure 4).
3. Mémoire morte électriquement commutable selon la revendication 1 ou 2, caractérisé en ce que des lignes de commande ou d'alimentation de tension d'alimentation (par exemple c, tension à la masse, figure 4), disposées ensemble en rang ou en colonne, sont associées aux- dits éléments de couplage situés dans des rangs ou des colonnes contigues.
4. Mémoire morte électriquement commutable selon au moins des revendications précédentes, caractérisé en ce que lesdits éléments de couplage sont constitués de structures de transistors à effet de champ intégrés qui comportent dans la zone de canal entre la source (N2) et le Drain (N1, N3) et sous les jonctions entre les parties de porte voisines (par exemple 4, 5; 22, 27), des régions de dopage (N12, N23) qui contribuent à la formation du canal.
5. Mémoire morte électriquement commutable selon au moins une des revendications précédentes, caractérisé en ce que lesdites parties de porte (par exemple 20, 21; 4, 5; 22, 27) desdits éléments de couplage (12, 3, 9) sont composées de silicium polycristallin.
6. Mémoire morte électriquement commutable selon au moins une des revendications précédentes, caractérisé en ce que lesdites lignes de commande (c, c) permettant la sélection de fonction sont composées de silicium polycristallin.
7. Mémoire morte électriquement commutable selon la revendication 6, caractérisé en ce que les bandes de silicium (poly 2) représentant lesdites lignes de commande (c, c) sont disposées au-dessus des bandes de dopage (N1, N2, N3) des Source et Drain des transistors à effet de champ.
8. Mémoire morte électriquement commutable selon au moins une des revendications 5 à 7, caractérisé en ce que lesdites parties de porte (par exemple 20, 21, 4, 27) connectées auxdites entrées (par exemple B, C, figure 5) sont réalisées sous la forme d'une première couche de polysilicium (poly 1) et lesdites lignes de commande (c, c) et les parties de porte que leur sont connectées (par exemple 5, 22) sont réalisées sous la forme d'une seconde couche de polysilicium (Poly 2).
9. Mémoire morte électriquement commutable selon au moins une des revendications précédentes, caractérisé en ce que les lignes connectées avec lesdites entrées (par exemple B, C figure 5) sont réalisées comme conducteurs métalliques (par exemple 25) qui sont connectées par des contacts (23, 24, 26, 28) avec lesdites parties de porte associées (20, 21, 4, 27) en polysilicium (Poly 1).
10. Utilisation d'une mémoire morte électriquement commutable selon au moins une des revendications précédentes dans un composant de processeur comportant des fonctions intégrées de circuits logiques programmables, en particulier pour mettre en oeuvre une architecture de système modifiable sans interruption, par exemple une architecture double.
EP80106964A 1980-11-12 1980-11-12 Mémoire morte électriquement commutable Expired EP0051693B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE8080106964T DE3070786D1 (en) 1980-11-12 1980-11-12 Electrically switchable read-only memory
EP80106964A EP0051693B1 (fr) 1980-11-12 1980-11-12 Mémoire morte électriquement commutable
JP56128251A JPS5837637B2 (ja) 1980-11-12 1981-08-18 電気的に切換え可能な読取り専門記憶装置
US06/317,669 US4445202A (en) 1980-11-12 1981-11-02 Electrically switchable permanent storage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP80106964A EP0051693B1 (fr) 1980-11-12 1980-11-12 Mémoire morte électriquement commutable

Publications (2)

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EP0051693A1 EP0051693A1 (fr) 1982-05-19
EP0051693B1 true EP0051693B1 (fr) 1985-06-19

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US (1) US4445202A (fr)
EP (1) EP0051693B1 (fr)
JP (1) JPS5837637B2 (fr)
DE (1) DE3070786D1 (fr)

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Publication number Publication date
US4445202A (en) 1984-04-24
JPS5837637B2 (ja) 1983-08-17
JPS5788597A (en) 1982-06-02
EP0051693A1 (fr) 1982-05-19
DE3070786D1 (en) 1985-07-25

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