EP0106458A2 - Verfahren zur Herstellung einer Halbleiteranordnung mit einem Feldeffekttransistor mit isoliertem Gate - Google Patents

Verfahren zur Herstellung einer Halbleiteranordnung mit einem Feldeffekttransistor mit isoliertem Gate Download PDF

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Publication number
EP0106458A2
EP0106458A2 EP83304843A EP83304843A EP0106458A2 EP 0106458 A2 EP0106458 A2 EP 0106458A2 EP 83304843 A EP83304843 A EP 83304843A EP 83304843 A EP83304843 A EP 83304843A EP 0106458 A2 EP0106458 A2 EP 0106458A2
Authority
EP
European Patent Office
Prior art keywords
film
pattern
gate electrode
self
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP83304843A
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English (en)
French (fr)
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EP0106458B1 (de
EP0106458A3 (en
Inventor
Katsuhiro Kawabuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Publication of EP0106458A2 publication Critical patent/EP0106458A2/de
Publication of EP0106458A3 publication Critical patent/EP0106458A3/en
Application granted granted Critical
Publication of EP0106458B1 publication Critical patent/EP0106458B1/de
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing an integrated circuit including a MIS field-effect transistor.
  • word lines for transmitting address data to memory cells are often made of the same material as that of a gate electrode of a MISFET.
  • a cell array 1 of an integrated circuit basically consists of cells 2, word lines 3 and bit lines 4.
  • the word lines 3 are connected to a gate electrode of each transistor called a transfer transistor.
  • polycrystalline silicon is used for the gate electrode. Accordingly, the word lines 3 are often also made of polycrystalline silicon.
  • diffusion layers for sources or drains which have the opposite conductivity type compared to the semiconductor substrate may also serve as the bit lines 4, or as power supply lines or ground lines.
  • a short response time is of prime importance in integrated circuits.
  • delay (RC delay) in data transmission due to wiring resistance has prevented such a short response time. That is, the polycrystalline silicon constituting the word lines is'electrically a semiconductor and therefore has a relatively high resistance.
  • Such a high resistance of polycrystalline silicon results in a delay in data transmission through the word lines and hence a delay in signal transmission of an integrated circuit.
  • diffusion layers for sources or drains are used as bit lines, power supply lines or ground lines, a similar problem is encountered, since the diffusion layers are also electrically semiconductors.
  • one proposal is to use an aluminum gate electrode.
  • aluminum has a melting point which is as low as 660°C, it cannot withstand annealing for formation of diffusion layers. Accordingly, this proposal is impractical.
  • the remaining insulation layer may be selectively removed to-form an opening exposing the impurity region and metal film may be formed on the exposed gate electrode pattern and the impurity region.
  • annealing may be performed to activate the impurity in the impurity region.
  • a gate electrode film of polycrystalline silicon or the like is formed, an impurity of an opposite conductivity type is doped into a substrate and annealing is performed, a low-resistance metal film of aluminum or the like is formed on the gate electrode film. Therefore, the resistance of the gate electrode can be sufficiently decreased, and thermal melting of the metal film can be prevented. For this reason, a response time of an integrated circuit having a word line of the same material as that of the gate electrode can be significantly improved.
  • a thick insulation layer, thicker than the gate electrode film remains at the side of the gate electrode film. Thus, the metal film can be formed on the gate electrode film in self-alignment therewith.
  • the metal film can be formed on the impurity region such as a source and drain. Accordingly, the response time of an integrated circuit using impurity regions formed in a semiconductor substrate as bit lines, electrode lines or ground lines can be significantly improved.
  • a gate insulation film 12 consisting of 0 silicon dioxide is formed to a thickness of 400 A by thermal oxidation of a p-type (100) silicon substrate 11 having a resistivity of 10 ⁇ -cm.
  • a gate electrode film 0 13 of polycrystalline silicon of 2,000 A thickness and 0 a self-alignment film 14 of silicon nitride of 5,000 A thickness are formed over the gate insulation film 12 by chemical vapor deposition.
  • the silicon nitride film 14 and the polycrystalline silicon film 13 are selectively etched into a gate electrode shape as shown in Fig. 2(b). Ion-implantation of arsenic into the substrate 11 is performed using the silicon nitride film 14 and the polycrystalline silicon film 13 as a mask, thereby forming source and drain regions 15a and 15b.
  • an insulation layer 16 of silicon dioxide is formed to a thickness of 7,000 A on the entire surface of the substrate by chemical vapor deposition.
  • a photoresist film 17 is spin coated to a thickness of 2 pm on the silicon dioxide layer 16 to give a level surface to the film 17.
  • annealing at 1,000°C is performed to activate the source and drain regions 15a and 15b.
  • the reactive ion etching technique using a mixture gas of CH 4 and H 2 as a reaction gas, the photoresist film 17 and the silicon dioxide film 16 are entirely etched until the silicon nitride film 14 is exposed, as shown in Fig. 2(d).
  • the silicon nitride film 14 is removed using phosphoric acid as shown in Fig. 2(e).
  • the top surface of the polycrystalline silicon film l3 is exposed and the side surfaces thereof are surrounded by the thick silicon dioxide layer 16 which is thicker than the film 13.
  • An aluminum film 18 having a thickness of 5,000 A is deposited by vapor deposition on the entire surface of the substrate as shown in Fig. 2(f). Then, a photoresist film 19 is spin coated to a thickness of 2 pm to give a level surface to the film 19.
  • the photoresist film 19 and the aluminum film 18 are etched until the silicon dioxide layer 16 is exposed, as shown in Fig. 2(g). Thus, the aluminum film 18 remains only on the polycrystalline silicon film 13.
  • a silicon dioxide film 21 is formed by chemical vapor deposition (CVD) on the entire surface of the silicon substrate 11 including the silicon dioxide layer 16 and the aluminum film 18.
  • CVD chemical vapor deposition
  • contact holes 22 are formed which respectively expose the source region 15a, the drain region 15b and the aluminum film 18.
  • a further aluminum layer is formed on the entire surface and is selectively etched to form an aluminum wiring pattern 23, thereby providing a desired MOS transistor.
  • a low-resistance aluminum film 18 can be formed on the polycrystalline silicon film 13 as a gate electrode in self-alignment therewith.
  • the resistance of the gate electrode serving also as a word line can be significantly reduced, thereby improving the response time of the integrated circuit.
  • the resistance of the gate electrode can be lowered to 1/10 or less of the conventional value by formation of the aluminum film 18. Since no annealing for activation of the impurity doped in the substrate is required after formation of the aluminum film 18, the aluminum film 18 will not melt during subsequent steps.
  • Figs. 3(a) to 3(e) are sectional views showing steps of a method for manufacturing an integrated circuit according to another embodiment of the present invention.
  • the same reference numerals as used in Figs. 2(a) to 2(j) denote the same parts referred to in Figs. 3(a) to 3(e), and a detailed description thereof will be omitted.
  • the second embodiment differs from the first embodiment in that a metal film is formed on the source and drain regions 15a and 15b and is connected thereto.
  • the manufacturing steps up to Fig. 2(e) remain the same in this embodiment.
  • the silicon dioxide film 16 and the gate insulation film 12 are selectively removed to form openings 31a and 31b, as shown in Fig.
  • the aluminum film 18 and the photoresist film 19 are formed as shown in Fig. 3(b).
  • the reactive ion etching technique By the reactive ion etching technique, the aluminum film 18 and the photoresist film 19 are etched until the silicon dioxide layer 16 is exposed.
  • the aluminum film 18 is selectively left on the polycrystalline silicon film 13, the source region 15a and the drain region 15b.
  • a silicon dioxide film 32 is formed by the plasma growth technique as shown in Fig. 3(d).
  • Contact holes are formed and an aluminum wiring pattern 33 is formed as shown in Fig. 3(e) to complete a MOS transistor.
  • the aluminum film 18 can be formed on the polycrystalline silicon film 13 as a gate electrode film in self-alignment therewith. At the same time, the aluminum film 18 can also be formed on the source and drain regions 15a and 15b in self-alignment therewith.
  • the second embodiment has the same effect as that of the first embodiment.
  • the impurity regions 15a and 15b are used as bit lines, power supply lines, or ground lines
  • the aluminum film 18 is in contact with these regions 15a and 15b and is present thereabove. As a consequence, the resistances of these regions can be reduced, and the response time can be improved.
  • the metal wiring layer formed on the source and drain regions 15a and 15b has a bilayered structure of the aluminum film 18 and an aluminum wiring pattern 33. Even if the contact holes are deep, disconnection will not occur and formation of the aluminum wiring pattern is easy.
  • the metal film is not limited to an aluminum film but may consist of any metal which has a high melting point but reacts at a high temperature, such as tungsten, tantalum, molybdenum or titanium.
  • the self-alignment film may consist.of any substance other than silicon nitride, e.g., silicon oxynitride, that has a high melting point and is nonreactive. Formation of source and drain regions is not limited to ion-implantation but may be extended to thermal diffusion.
  • the method for selectively etching the insulation layer on the self-alignment film may be a method which does not use a leveling film such as a photoresist film, but comprises a method for filling the troughs of the insulation layer with a film which has the same etching rate.
  • a leveling film such as a photoresist film

Landscapes

  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
EP83304843A 1982-08-25 1983-08-22 Verfahren zur Herstellung einer Halbleiteranordnung mit einem Feldeffekttransistor mit isoliertem Gate Expired EP0106458B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP147055/82 1982-08-25
JP57147055A JPS5941870A (ja) 1982-08-25 1982-08-25 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
EP0106458A2 true EP0106458A2 (de) 1984-04-25
EP0106458A3 EP0106458A3 (en) 1986-07-16
EP0106458B1 EP0106458B1 (de) 1989-11-08

Family

ID=15421474

Family Applications (1)

Application Number Title Priority Date Filing Date
EP83304843A Expired EP0106458B1 (de) 1982-08-25 1983-08-22 Verfahren zur Herstellung einer Halbleiteranordnung mit einem Feldeffekttransistor mit isoliertem Gate

Country Status (4)

Country Link
US (1) US4514233A (de)
EP (1) EP0106458B1 (de)
JP (1) JPS5941870A (de)
DE (1) DE3380836D1 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2582445A1 (fr) * 1985-05-21 1986-11-28 Efcis Procede de fabrication de transistors mos a electrodes de siliciure metallique
EP0287385A3 (de) * 1987-04-17 1988-12-07 Tektronix Inc. Verfahren zur Herstellung eines Feldeffekttransistors
EP0303061A3 (en) * 1987-08-13 1989-04-26 International Business Machines Corporation Process for forming a planarized, metal-strapped polysilicon gate fet
FR2622355A1 (fr) * 1987-10-22 1989-04-28 Mitsubishi Electric Corp Procede de fabrication d'un transistor a effet de champ a porte schottky

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US4985373A (en) * 1982-04-23 1991-01-15 At&T Bell Laboratories Multiple insulating layer for two-level interconnected metallization in semiconductor integrated circuit structures
JPS61145868A (ja) * 1984-12-20 1986-07-03 Toshiba Corp 半導体装置の製造方法
GB2172427A (en) * 1985-03-13 1986-09-17 Philips Electronic Associated Semiconductor device manufacture using a deflected ion beam
US4972251A (en) * 1985-08-14 1990-11-20 Fairchild Camera And Instrument Corp. Multilayer glass passivation structure and method for forming the same
US4654121A (en) * 1986-02-27 1987-03-31 Ncr Corporation Fabrication process for aligned and stacked CMOS devices
JPS63268258A (ja) * 1987-04-24 1988-11-04 Nec Corp 半導体装置
US5171718A (en) * 1987-11-27 1992-12-15 Sony Corporation Method for forming a fine pattern by using a patterned resist layer
US4908332A (en) * 1989-05-04 1990-03-13 Industrial Technology Research Institute Process for making metal-polysilicon double-layered gate
US5378650A (en) * 1990-10-12 1995-01-03 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and a manufacturing method thereof
US5885879A (en) * 1997-03-21 1999-03-23 Advanced Micro Devices, Inc. Thin polysilicon masking technique for improved lithography control
US5930634A (en) * 1997-04-21 1999-07-27 Advanced Micro Devices, Inc. Method of making an IGFET with a multilevel gate
US5953612A (en) * 1997-06-30 1999-09-14 Vlsi Technology, Inc. Self-aligned silicidation technique to independently form silicides of different thickness on a semiconductor device
US6074921A (en) * 1997-06-30 2000-06-13 Vlsi Technology, Inc. Self-aligned processing of semiconductor device features
US6143613A (en) * 1997-06-30 2000-11-07 Vlsi Technology, Inc. Selective exclusion of silicide formation to make polysilicon resistors
US6207543B1 (en) 1997-06-30 2001-03-27 Vlsi Technology, Inc. Metallization technique for gate electrodes and local interconnects
US6194299B1 (en) * 1999-06-03 2001-02-27 Advanced Micro Devices, Inc. Method for fabrication of a low resistivity MOSFET gate with thick metal on polysilicon
CN109817586A (zh) * 2018-12-25 2019-05-28 厦门市三安集成电路有限公司 高温退火时保护功率器件金属接触的方法和金属接触结构

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GB1522755A (en) * 1975-07-25 1978-08-31 Ncr Co Method of manufacturing a semiconductor device
JPS5235983A (en) * 1975-09-17 1977-03-18 Hitachi Ltd Manufacturing method of field effective transistor
IT1089298B (it) * 1977-01-17 1985-06-18 Mostek Corp Procedimento per fabbricare un dispositivo semiconduttore
JPS53144687A (en) * 1977-05-23 1978-12-16 Matsushita Electric Ind Co Ltd Production of semiconductor device
US4141022A (en) * 1977-09-12 1979-02-20 Signetics Corporation Refractory metal contacts for IGFETS
US4149307A (en) * 1977-12-28 1979-04-17 Hughes Aircraft Company Process for fabricating insulated-gate field-effect transistors with self-aligned contacts
US4282647A (en) * 1978-04-04 1981-08-11 Standard Microsystems Corporation Method of fabricating high density refractory metal gate MOS integrated circuits utilizing the gate as a selective diffusion and oxidation mask
JPS5561037A (en) * 1978-10-31 1980-05-08 Toshiba Corp Preparation of semiconductor device
JPS55112853U (de) * 1979-02-02 1980-08-08
JPS55125649A (en) * 1979-03-22 1980-09-27 Nec Corp Production of semiconductor integrated circuit
JPS55125651A (en) * 1979-03-22 1980-09-27 Nec Corp Production of semiconductor integrated circuit
FR2461360A1 (fr) * 1979-07-10 1981-01-30 Thomson Csf Procede de fabrication d'un transistor a effet de champ du type dmos a fonctionnement vertical et transistor obtenu par ce procede
JPS5642372A (en) * 1979-09-12 1981-04-20 Toshiba Corp Manufacture of semiconductor device
JPS5658247A (en) * 1979-10-17 1981-05-21 Fujitsu Ltd Production of semiconductor device
US4343082A (en) * 1980-04-17 1982-08-10 Bell Telephone Laboratories, Incorporated Method of making contact electrodes to silicon gate, and source and drain regions, of a semiconductor device
US4400867A (en) * 1982-04-26 1983-08-30 Bell Telephone Laboratories, Incorporated High conductivity metallization for semiconductor integrated circuits

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2582445A1 (fr) * 1985-05-21 1986-11-28 Efcis Procede de fabrication de transistors mos a electrodes de siliciure metallique
WO1986007190A1 (fr) * 1985-05-21 1986-12-04 Societe Pour L'etude Et La Fabrication De Circuits Procede de fabrication de transistors mos a electrodes de siliciure metallique
EP0287385A3 (de) * 1987-04-17 1988-12-07 Tektronix Inc. Verfahren zur Herstellung eines Feldeffekttransistors
US4826782A (en) * 1987-04-17 1989-05-02 Tektronix, Inc. Method of fabricating aLDD field-effect transistor
EP0303061A3 (en) * 1987-08-13 1989-04-26 International Business Machines Corporation Process for forming a planarized, metal-strapped polysilicon gate fet
FR2622355A1 (fr) * 1987-10-22 1989-04-28 Mitsubishi Electric Corp Procede de fabrication d'un transistor a effet de champ a porte schottky
US4843024A (en) * 1987-10-22 1989-06-27 Mitsubishi Denki Kabushiki Kaisha Method of producing a Schottky gate field effect transistor
GB2211350A (en) * 1987-10-22 1989-06-28 Mitsubishi Electric Corp A method of producing a schottky gate field effect transistor
GB2211350B (en) * 1987-10-22 1992-02-12 Mitsubishi Electric Corp A method of producing a schottky gate field effect transistor

Also Published As

Publication number Publication date
EP0106458B1 (de) 1989-11-08
EP0106458A3 (en) 1986-07-16
JPH0576177B2 (de) 1993-10-22
US4514233A (en) 1985-04-30
DE3380836D1 (en) 1989-12-14
JPS5941870A (ja) 1984-03-08

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