Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
  • G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
  • G01K7/16—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements
  • G01K7/18—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements the element being a linear resistance, e.g. platinum resistance thermometer
  • G01K7/20—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements the element being a linear resistance, e.g. platinum resistance thermometer in a specially-adapted circuit, e.g. bridge circuit

Definitions

• This invention relates generally to circuitry for measuring temperature and, more particularly, to bridge circuitry utilizing precision resistance thermometers for providing automatic measurement of temperature.
• SPRT platinum resistance thermometers
• IPTS International Practical Temperature Scale
• a basic bridge circuit utilizes constant current reference circuitry for providing a 15 constant reference current through a precision reference resistance and through a standard platinum resistance thermometer (SPRT) element.
• the voltage across the SPRT element is supplied to a fixed-gain amplifier circuit the output of which is in turn supplied to a digital-to-analog (D/A) measurement circuitry.
• D/A digital-to-analog
• the 20 D/A circuit permits an effective determination of the ratio of the .. output from the fixed-gain amplifier circuit and a reference voltage across a known reference resistance in the constant current reference circuit.
• the resistance of the standard platinum resistance thermometer can then be determined in terms of 25 the value of the fixed-gain of the fixed-gain amplifier circuit, ;.7 the value of the reference resistance, and the value of such voltage ratio.
• Such circuitry provides for a completely automated measurement of the SPRT resistance with 30 very high accuracy, which resistance can be readily converted ;- * . using appropriate micro-processor circuitry, for example, to a temperature reading which has an extremely low error.
• the overall circuitry is designed so that suitable solid state switches and transformers of relatively simple construction can be used,
• FIG. 1 depicts a block diagram of an embodiment of the invention
• FIG. 2 depicts a more specific partial block and partial schematic diagram of the embodiment of FIG. 1;
• FIG. 3 depicts a more specific partial block and partial schematic diagram of a portion of the embodiment of FIG. 1;
• FIG. 4 depicts a timing diagram helpful in explaining the operation of FIG. 3;
• FIG. 5 depicts the interconnection of the reference circuit of FIG. 1;
• FIG. 6 depicts a partial block and partial schematic diagram showing more particularly the D/A converter of FIGS. 1 and 2;
• FIG. 7 depicts in diagrammatic form the switches used in the D/A converter of FIG. 6;
• FIG. 8 depicts a partial block and partial schematic diagram showing the automatic quadrature balance circuitry of FIG. 3.
• AC source 10 supplies an AC voltage through a primary winding HA of a first stage of a transformer 11, the secondary winding 11B of which provides a drive voltage Erj to a reference current circuit 12 which in turn supplies a constant current IREF to a standard platinum resistance thermometer (SPRT) element 14 having a resistance R-j* which is proportional to the temperature.
• SPRT platinum resistance thermometer
• the voltage ET; across SPRT element 14 is supplied to a
• fixed-gain AC feedback amplifier circuit 15 (identified as having a fixed-gain Gp) which produces an output voltage Ej j .
• Such voltage is supplied to D/A measurement circuit 16 which is arranged so that when a plurality of switches therein are suitably set (as discussed in more detail below), the voltage E a therefrom can be made substantially equal to the voltage E_ .
• the reference circuit 12 includes a reference resistance 13 through which the current IREF flows, the voltage across such reference resistance being designated as Ejj-gp.
• the voltage Ex across SPRT element 14 can be defined by the current therethrough and the resistance thereof as
• thermometer element Since the resistance of reference resistor 13 and the gain of amplifier 15 are known and predetermined, if the ratio of the voltages E * -,/EREP can be determined, the resistance of the thermometer element can also be determined.
• the resistance of SPRT element 14 can be
• the resistance of the SPRT element 14 can be calculated (using suitable computational logic such as available through the use of a microprocessor) from the known values of R EF an d Gp and from the value of the ratio
• E a/EREF suitably determined from the settings of the switches in the D/A measurement circuit 16.
• the microprocessor can thereupon determine the temperature in accordance with the known International Practical Temperature Scale which defines the relationship between the SPRT resistance R and temperature.
• FIG. 2 A more specific configuration of an overall resistance thermometer circuit is shown in FIG. 2 in which AC source 10 is a suitable sine wave oscillator 20 which supplies the primary winding HA of the first stage of transformer 11 with a sine wave signal at a suitably selected frequency which in the particular embodiment being described herein, for example, is 384 Hz.
• the secondary winding 11B of transformer 11 provides the input drive voltage E_ for the reference current circuit 12 which includes reference resistor 13 and a standard platinum resistance thermometer 14 as shown.
• the reference winding 11C of the second stage of transformer 11 and a high gain AC feedback amplifier 18 are connected as shown so that the current IREF through SPRT
• SUBSTITUTE SHEET 14 is constant and provides a voltage E thereacross.
• the voltage Ex is supplied to fixed-gain AC feedback amplifier circuit 15.
• Such circuitry includes an input transformer 22, op-amp 23 and output transformer 25.
• a feedback winding 26 of output transformer 25 provides the output voltage E5 of circuit 15.
• a specific circuit for implementing the fixed-gain AC feedback amplifier circuitry 15 of FIG. 2 is described in my copending application, Serial No. , entitled "Band-Pass Amplifier
• the D/A measurement circuit 16 comprises a first two-stage transformer having stages identified as T ⁇ a and T15 in FIG. 2 followed by a second two-stage transformer having stages identified as ⁇ 2 a and ⁇ 2b in FIG. 2.
• the settings of variable winding 11D of stage Tj]-, and of variable winding HE of stage ⁇ 2 as determined by control logic 18 produces the desired voltage E a .
• E a -E ⁇ When (E a -E ⁇ ) is effectively reduced to zero, such voltages are equal as desired.
• E a to E EF can be determined in accordance with the number of turns on windings 11C, HD and HE as follows:
• N a are the turns on winding HD of T__ , fc, are the turns on winding HE of T25, NREJ ⁇ are the turns on winding HC of T ⁇ *-, and k is the stepdown ratio of Tj to
• the number of turns N a and N ⁇ are determined by the settings of a plurality of FET switches (discussed in more detail below for a specific embodiment of the D/A circuit 16) represented in FIG. 2 by settings S a and S_ . Such settings are controlled by control logic 18 which utilizes a successive
• circuitry during the first mode of operation is to provide to a successive approximation register
• SUBSTITUTE SHEET E a will be in phase or 180° out of phase depending on whether E j , is greater or less than E a .
• Such "error" signal is amplified in a preamplifier 30, detected in the phase sensitive detector 31 and the resulting DC signal is then applied to a relatively fast "finite" time integrator 32 the output thereof being supplied to a comparator OP-AMP 33.
• the reset switch Sj of the integrator circuit is momentarily closed to reset the integrator at the beginning of each clock pulse to the successive approximation register.
• the time constant of he integrator is selected (e.g., 100 microseconds) and the clock frequency is one-half the bridge excitation frequency.
• the output of the comparator is applied to the data input of the SAR thus determining the setting of the switches in the D/A circuit (shown in more detail in FIG. 6) and, hence, drives the output of the D/A circuit towards equality with the bridge output.
• Such setting represents the most significant bits of the binary number, the decimal equivalent of which is proportional to the desired ratio
• the analog output represented by the residual error signal (E e ) remaining after the first mode of operation has been completed has been converted to a binary output using a dual slope integrator 36, as discussed in the aforesaid depending application and as also described in copending application Serial No. 147,220, filed on May 6, 1980.
• the mode switches S ⁇ a through S ⁇ are set to position 2. In such position the residual error signal is amplified by the preamplifier and the band pass amplifier 34 in cascade, and synchronous detector 31 is connected to the output of the band pass amplifier.
• SUBSTITUTE SHEET T2 is used to allow the band pass amplifier, the synchronous detector 31 and the Bessel filter 35 to stabilize.
• the dual slope integrator 36 is maintained at zero output by opening switch S e and closing reset switch Sf.
• the output of the Bessel filter is a steady DC voltage proportional to E e .
• switches S e and Sf are reversed resulting in the output of the dual slope integrator providing a ramp output signal at a rate and in a direction depending on the magnitude and phase of the error signal, as shown in FIG. 4.
• switch S e opens and S c is set by the control logic to either position 2 or position 3, depending on the polarity of the output of the dual slope integrator.
• the switch S e is closed resulting in the dual slope integrator providing an output which ramps back towards zero voltage.
• the time interval T5 is proportional to the residual error signal and is measured from the end of T4 to the time of zero crossing as detected by the comparator OP-AMP 33.
• a clock output of a selected frequency is generated by means of an appropriate clock circuit (such a circuit may utilize a phase-lock loop frequency multiplier locked to the 387 Hz. bridge excitation signal, for example).
• Such clock signal is gated to the input of a suitable binary counter (not shown during T5 thereby resulting in a count which is proportional to such time interval. Since changes in gain of any of the circuits described in FIG. 3 affect both E e and E r equally, they have no real effect on the final result.
• SUBSTITUTE SHEET amplifier 34 the phase sensitive detector 31 and the low pass Bessel filter 35, as well as the finite time integrator 32 and the dual slope integrator 36 is shown in the aforesaid copending application, Serial No. , filed concurrently herewith, and need not be described in greater detail here.
• the AC feedback amplifier 18 has a very high open loop gain (e.g., in a particular embodiment an open loop gain of 2.5 x 10') at the operating frequency of the circuit (384Hz.) and has an amplitude and phase response with frequency which permit it to operate in a closed loop with 100% feedback with excellent stability.
• a suitable reference current IR F of ••• mA » f° r example, can be obtained by making EREF equal to 10 volts (rms) and RREF equal to 10,000 ohms.
• the output of AC feeedback amplifier 18 will be 0.125 volts and the input will be 5 x 10 ⁇ 9 volts. Consequently, the open circuit voltage between the voltage terminal of the reference resistor and ground will differ from the open circuit voltage between Vj and V2 across RREF by only one part in 5 x lO -** - ⁇ .
• the reference voltage E F clearly represents an accurate version of the voltage across the reference resistance.
• the reference resistor can be, for example, a 10,000 ohms oil filled metal film on glass type resistor made by Vishay Corporation of Malvern, Pennsylvania. Such a reference resistance is temperature controlled to within ⁇ 0.003°C.
• FIG. 5 shows in more detail how the reference current circuit is interconnected.
• the coaxial connections used as shown therein considerably reduce errors due to inductive effects and noise pickup from all external sources. Also, the method of interconnection was selected so that the capacitance of the coaxial leads does not affect the operating results of the circuit since such capacitance is in parallel with a very low impedance source such as the output of AC feedback amplifier 18, and is also
• the reference current circuit will cause a reference current IREF to flow through the SPRT which is very accurately given by the ratio of EREF/ R REF-
• the reference voltage circuit consists of the second stage transformer winding HC in parallel with the voltage terminal ** --' Vi of the reference resistor and ground. Since this results in a small current flowing in V j , the reference voltage can be defined as the voltage between the reference junction J and ground (see FIG. 5). It can be shown that the output voltage E ⁇ across any winding W n is given by 0
• R 11C are winding resistances as shown in FIG. 5.
• Z is the excitation impedance of transformer stage T _ (FIG. 2).
• R-Q + RQB 0.75 ohms, R ⁇ 2 +
• the voltage E n (i.e. the voltage across winding HD for any particular setting S a - FIG. 2) is equal to the reference voltage EREF times the turns ratio W ⁇ /WREF of the winding HC to the reference winding HB * j_.
• a D/A measurement circuit 15 is shown in FIG. 6 as comprising a two-stage transformer (T ⁇ a and T _ ) having, in the particular version described, six output windings S * through S of 32, 16, 8, 4, 2, and 1 turns forming six bits.
• a second two-stage transformer has two input windings W * and W2, each having 128 turns, driven by single turn output windings on the first two-stage transformer. Consequently, the output voltage on winding W3 of 64 turns on the second transformer is one-half the output on winding W4 of the first two-stage transformer, thus continuing the binary weighted ratios on the 7 windings of the second two-stage transformer to form a a total of 13 binary stages.
• the states of switches S]_ through S13 in FIG. 6 represent the binary value of the sum of the 13 voltages across such windings.
• the D/A converters are current summing devices.
• Each of the switches can be, for example, implemented by a pair
• each of the switches Si - S13 can be equivalently formed of such FET pair.
• the FET of each pair is turned ON or OFF directly by its associated control line from control logic 18 while the other is driven to the opposite state by inverting the control line logic as shown in FIG. 7.
• Appropriate transistors of the VMOS type can be utilized such as those sold under the model designation IVN 5001AND made and sold by Intersil Corporation of
• the overall digitization process is controlled by conventional logic and timing circuits. Other logic operations are controlled by a microprocessor which can be used to set up the bridge for a selected mode of operation, to start the digitization process, to read and process the data when the digitization is complete. Processed data can be displayed or transmitted to external devices via optional interfaces within the skill of the art. Microprocessors as known can be controlled by manual inputs to a front panel keypad, for example, or optionally controlled by external devices through appropriate interfaces. Thus, in a particular embodiment the initial successive approximation measurement provides 13 most significant bits while the second measurement (dual slope integration) provides 13 least significant bits so as to produce an overall 26-bit bridge output which can be converted to the resistance in accordance with the following equation:
• Conversion of the resistance to temperature is accomplished by the standard IPTS-68 equations for SPRT operation.
• a microprocessor can perform the calculation of resistance to temperature while the bridge is digitizing.
• a quadrature component in the error signal E e can cause errors despite the fact that the phase sensitive detector 312 as shown in FIG. 3 theoretically has zero response to quadrature. For example, if such quadrature component is large enough it can cause an overload in the band pass amplifier or detector which results in non-linear operation with erroneous response to small in-phase signals.
• an automatic quadrature balancing circuit 37 as shown in FIG. 3 can be used.
• a particular embodiment of such a circuit is shown in more detail in FIG. 8 and represents a negative feedback loop which forces the quadrature component of the input voltage to zero at the output without modifying the in-phase component.
• the input voltage is supplied to the positive input of an OP-AMP 40 utilizing a tuned circuit 41 which provides a broadly tuned amplifier which results in an input to a linear analog multiplier 42.
• the other input to the multiplier is a sine wave voltage which is in exact quadrature with the bridge input voltage which is obtained as a quadrature reference input from the bridge reference signal.
• the output of multiplier 42 will contain a DC component which is exactly proportional to the quadrature component at the other input to multiplier 42. Such DC component causes the integrator circuit 43 to change.
• the output of the integrator is an input to a second multiplier 44 (substantially identical to multiplier 42) the other input of which is also the quadrature sine wave signal.
• the output of multiplier 44 will be a quadrature voltage

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• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Measurement Of Resistance Or Impedance (AREA)
• Measurement Of Current Or Voltage (AREA)

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• 1983
  • 1983-09-23 CA CA000437414A patent/CA1205650A/en not_active Expired
  • 1983-09-24 EP EP19830903441 patent/EP0120943A4/de not_active Ceased
  • 1983-09-24 WO PCT/US1983/001487 patent/WO1984001218A1/en not_active Ceased

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