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• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/85—Complementary IGFETs, e.g. CMOS
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/50—Physical imperfections
  • H10D62/53—Physical imperfections the imperfections being within the semiconductor body 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/85—Complementary IGFETs, e.g. CMOS
  • H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
  • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
  • H10P30/212—Through-implantation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P36/00—Gettering within semiconductor bodies
  • H10P36/03—Gettering within semiconductor bodies within silicon bodies
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
  • H10P95/40—Treatments of semiconductor bodies to modify their internal properties, e.g. to produce internal imperfections
  • H10P95/402—Treatments of semiconductor bodies to modify their internal properties, e.g. to produce internal imperfections of silicon bodies

Definitions

• the present invention generally relates to high density CMOS FET devices and integrated circuits, and the fabrication of such, and, in particular, to high density CMOS FETs having residual defects particularly associated with source and drain regions formed in a multiple retrograde doping profile well structure that essentially eliminates the occurrence of latch-up during operation.
• latch-up is characteri zed as a high current condition wherein the device is irreversibly latched into a single electrical state typically preventing the entire circuit from functioning properly and resulting in device damage , i f not complete destruction .
• the latch-up condition is generally attributed to the presence and unde sirable function of parasitic bipolar transistors inherently formed in the CMOS FET structure .
• the con figuration of the parasitic bipolar transistors is such that a closed loop feedback path typically having a gain greater than one exists ; -
• random, atypical operational conditions are encountered, such as electrical transients, regenerative feedback occurs with a resultant latch-up of the device's electrical state.
• CMOS latch-up is a commonly recognized problem. See, for example, "The Physics and Modeling of Latch-up in CMOS Integrated Circuits," D. B. Estreich, Technical Report No. G-201-9, prepared under Defense Advanced
• Patent 4,318,750 and "Silicon-Gate C-MOS Chips Gain Immunity to SCR Latch-up", L. Walneman, Electronics, Vol. 56, No. 16, August 11, 1983, pp. 136-140.
• OMPI OMPI .
• the general purpose of the present invention is therefore to provide a CMOS device structure, and method of fabricating the structure, that is essentially immune to latch-up.
• an advantage of the present invention is that the parasitic feedback loop gain is reduced to approximately one or less by the localized inhibition of the operation of the parasitic bipolar transistors.
• Another advantage of the present invention is that there is no significant adverse affect to the desirable operational characteristics of a CMOS device provided in accordance with the present invention.
• a further advantage of the present invention is that it can be efficiently incorporated into any high density CMOS fabrication process.
• Still another advantage of the present invention is that a CMOS device provided in accordance with the present invention may be directly scaled without any adjustment of the design as would be necessary to include additional structures requiring substrate surface area.
• FIG. 1 is a cross section of a CMOS device structure to which the present invention is preferably applied, a circuit schematic of the parasitic bipolar transistor pair and their significant interconnection being shown as an overlay;
• FIG. 2 is a graphical representation of the doping density profile taken through a source or drain region, the well region, and the substrate of the preferred double retrograde well embodiment of the present invention.
• FIG. 1 A cross section of a CMOS FET structure, generally indicated by the reference numeral 6, is shown in FIG. 1.
• This CMOS structure constitutes the preferred embodiment of the present invention.
• the manner of the fabrication of the CMOS structure 6 and its operation are described at length in U.S. Patent Applications Serial No. 297,903, filed August 31, 1981, and Serial No. 523,815, filed August 15, 1983, both of which are assigned to the Assignee of the present invention. These applications are expressly incorporated herein by reference.' However, for purposes of clarity, the significant features of the CMOS structure 6 and the particular steps necessary for its fabrication will be described below.
• the CMOS FET structure 6 is comprised of a semi ⁇ conductor substrate 12, preferably silicon lightly doped to an N ⁇ type conductivity with phophorous at a concen ⁇ tration of approximately 5 x IO 14 cm"" 3 .
• Active devices wells 14, 16 are provided in the substrate 12 adjacent a top substrate surface. The wells 14, 16 are more heavily doped than the substrate 12, preferably with boron and phosphorous respectively, so as to form complementary P- and N-type wells. Highly doped P + and N + channel stops 26, 28 separate the twin-wells 14, 16.
• An N channel active device comprising heavily doped N + source and drain regions 18, 20, gate oxide layer 32, gate 34, and source region contact 40, is formed at the surface of the P-well 14.
• a complementary P channel active device generally indicated by the reference numeral 10, comprising heavily doped P + type drain and source regions 22, 24, gate oxide layer 36, gate 38 and source region contact 42, is provided at the surface of the N-well 16.
• the complemen- tary electrical operation of the CMOS FET structure 6 is insured by the provision of an electrical interconnection 46 between the two gates 34, 38 to which an input signal, V., is applied and by the provision of a common drain contact 44 from which an output signal, V Q , is obtained.
• the process by which the CMOS FET structure 6 is formed, in accordance with the above noted prior filed applications, is as follows:
• (j) define source and drain regions 18, 20 for the N channel device 8 and heavily implant N-type (e.g., arsenic) ions for the N source and drain regions 18, 20 by overcompen sating previously implanted boron atoms;
• N-type e.g., arsenic
• (k) define contact holes to each of the source and drain regions 18, 20, 22, 24 and form metal contacts 40, 42, 44.
• the vertical bipolar transistor 50 is typically an NPN device having the N-type substrate 12 as a collector, the P-well 14 as a base, and the N-type drain region 18 as an emitter coupled essentially to ground through the metal contact 40.
• the other bipolar transistor 52 is typically of a lateral PNP configuration having the P-type drain region 24 as an emitter, the N-well and, more generally, the substrate 12 as a base, and the P + channel stop 26 and P-well 14 as a collector.
• the parasitic bipolar transistors 50, 52 are conductively connected via conduc ⁇ tion paths 54, 56 essentially creating a current feedback loop.
• Latch-up occurs typically in response to a transient condition, such as a large voltage spike in the otherwise dc voltage potential provided as V DD to the P channel device source contact 42. Consequently, a large amount of current will begin to flow between the source 24 and the source 18 through the network formed by the parasitic bipolar transistors 50, 52 during latch-up.
• the CMOS FET device 6 ceases to operate as intended and, unless power to the device 6 is quickly removed, irreparable • * damage may and typically does occur.
• CMOS FET structure 6 of FIG. 1 The presence of a parasitic bipolar network is not unique to the CMOS FET structure 6 of FIG. 1. It is also not specific to CMOS FET structures formed in silicon substrates.. The presence of the parasitic bipolar network is also not specific to twin-well CMOS FET structures.
• the parasitic bipolar transistor network will occur in any CMOS FET structure formed in a continuous, even lightly conductive epitaxial or bulk substrate material; the structure being further characterized as having a shallow well region such as formed by ion implantation without a subsequent well drive-in diffusion. Generally, so long as there is a well region having a conductivity type opposite that- ' of the semiconductor material in which the structure is provided, both the vertical and the lateral parasitic bipolar transistors will be inherently pre sent .
• T us for the complementary case of a P conductivity substrate , an N-well is essential to provide the P channel FET device , resulting in the inherent formation of a vertical PNP bipolar tran- sistor parasitically coupled with a lateral NPN bipolar transi stor .
• CMOS FET structure that inherently does not include a parasitic bipolar network , and to which the present invention cannot be applied , occurs when compleraetary N and P channel FETs are separately provided in semiconductor islands electrically isolated from one another by insulator material such as silicon dioxide , semi-insulating gallium arsenide , or sapphire .
• the pre- sent invention provides a means of e ffectively reducing the current gain product g of the parasitic bipolar transi stors to less than one thereby providing a CMOS FET structure that is essentially immune to latch-up.
• the present invention is applicable to all such CMOS FET structures , as noted above , inherently posse ssing a parasitic bipolar network.
• the benefits of the present invention are obtained by the manner in which the essential well region (conduc ⁇ tivity type opposite that of the substrate ) is provided and by the manner in which the source and drain regions present therein are provided and subsequently thermally conditioned.
• the P-well region 14 of the preferred embodiment of the present invention is preferably provided by a plurality of ion implantations of P-type impurities , such as boron .
• the implant dosage and the implantation energy level are selected so as to provide separate and distinct pea ks in the carrier concentration l N D ⁇ N A 1 Profile as measured perpendicular from the
• OMPI NA substrate surface into the substrate 12 the retrograde peaks being separated by regions of relatively lower carrier concentration.
• Such a non uniform carrier concentration profile is hereby defined as a multiple retrograde doping profile.
• the multiple implants are preferably performed at energies ranging between approximately 100 and 600 keV so as to each provide a dosage of between approximately 1 x IO 13 and 5 x IO 13 cm -2 to form a multiple retrograde P-well in the N-type silicon substrate.
• Specific energy implant and dosage values, suitable for providing a corresponding number of retrograde peaks in the doping density profile, can be determined by simple and ordinary calculation and experimentation carried out with regard to the particular implant species and substrate material being used.
• two P-well implants are performed so as to provide a double retrograde doping density profile, substantially as shown in FIG. 2.
• the first implant is performed using boron as the preferred ion species at an energy between approximately 120 and 200 keV at a dosage of approximately 1 x IO 3 to 5 x IO-- 3 cm -2 .
• T e second implant again preferably using boron as the implant species, is performed at an energy of between approximately 340 to 500 keV also at a dosage of between approximately 1 x IO 13 to 5 x 10 13 cm" 2 .
• the surface of the substrate 12 overlying the P-well 14 is prepared in a conventional manner for the formation of the N channel device 8 source and drain regions 18, 20.
• P-type impurities are not implanted into the source and drain region 18, 20 areas of the N channel FET 8 as part of the provision of the source and drain regions 22, 24 of the P channel FET 10. Though an unnecessary process modification, this simplifies the process by obviating the need to overcompensate the P-type impurities in providing the N + source and drain regions 18, 20.
• These regions 18, 20 are preferably provided by a high-dose , low energy implant of N-type impurities.
• the implant energy is preferably between approximately 30 and 150 keV performed so as to provide a dosage of approxi ⁇ mately 5 x IO 15 cm -2 .
• the source and drain regions 18, 20 are then sub ⁇ jected to an annealing process step.
• the temperature and time within which this anneal is performed are selected so that the crystal defects created by the ion implantation of the source and drain regions 18, 20 are only partially removed. This can be accomplished in a variety of manners, including the use of a low temperature furnace anneal at approximately 800 to 875 ⁇ C for a total time of approx- imately 15 to 30 minutes or a transient anneal process utilizing an E-beam, laser, or flashlamp to raise the temperature of the substrate 12 to between approximately' 900 and 1000°C for a total period of between approximately 2 and 20 seconds.
• the CMOS FET 6 is preferably completed by exposing the surface portions of the source and drain regions 18, 20, 22,- 24, providing the source and drain contacts 40, 42, 44 to finally obtain the structure shown in FIG. 1 consistent with the above noted prior filed patents.
• the present invention operates to substantially reduce the current gain of the vertical bipolar transistor 50, reducing the current gain product $ p of both of the parasitic bipolar transistors 50, 52 to approximately one or less, and thereby insures immunity to latch-up.
• the current gain of the vertical bipolar transistor 50 is directly dependent on the injection efficiency of electrons from the source region 18 into and through the well region 14, the vertical bipolar transistor 50 being a minority carrier device and electrons being a minority carrier in an NPN bipolar structure.
• the present invention provides for residual defects to be associated with the source region 18 as a result of the incomplete annealing thereof. While the exact distribu- tion of hese residual defects is not known, the signifi ⁇ cant defects in substantial number lie in the deepest portion of the source region 18 (and the drain region 20) and the immediately underlying portion of the P-well 14. In operation, these residual defects act as minority charge carrier recombination centers and thereby effectively reduce the minority carrier injection efficiency into the P-well 14.
• the distribution of residual defects inherently does not lie within the channel region underlying the gate 34 of the N-FET device 8 due to the presence of the gate 34 during the source and drain 18, 20 implant. Further, though the greatest density of defects may initially lie at the surface of the source and drain regions 18, 20, the incomplete annealing will correspondingly have its greatest effect in removing these surface crystal defects. Thus, there is no significant number of residual surface defects. Also, as a majority carrier device, the N channel FET transistor 8 is relatively less sensitive to the presence of residual defects than bipolar transistors. Consequently, the electrical operation of the N channel FET device 8 is substantially if not completely unaffected by the residual defects introduced in accordance with the present invention.
• the multiple retrograde doping profile of the P-well region serves to reduce the transport efficiency of minority carriers therethrough in a number of ways.
• the minority carrier transport efficiency is directly reduced by an electric field associated with each of the retro ⁇ grade peaks of the doping profile.
• an electric field E is associated with the shallowest retrograde peak.
• the polarity of E is positive into the substrate 12 in the case of a NPN parasitic bipolar transistor 50.
• the electric field E is the inherent result of a local space charge difference arising as a result of the locally nonuniform (retro ⁇ grade) doping profile. Accordingly, a second electric field E2 is associated with the second retrograde peak of the doping profile.
• a CMOS FET device of the structure shown in FIG. 1 and having the double retrograde doping density profile shown in FIG. 2 has been fabricated in accordance with the present invention.
• the P-well was provided by two successive ion implantations, the first at approximately 120 keV and the second at approximately 340 keV, each to a dosage of approximately 1 x IO* cm" 2 .
• arsenic was then implanted at 80 keV and 150 keV to a total dosage of 5 x 10 15 cm -2 to form the source and drain regions of the N channel FET device.
• a transient anneal was then performed by rapidly rastor scanning the device substrate, thereby heating the substrate to approximately 1000 °C for a period of approximately 10 seconds. All other processing of the device to obtain the completed structure as shown in FIG. 1 was performed in accordance with that described above .
• the device produced has a P-well depth of approxi ⁇ mately 1.1 ym, source and drain region depths of approxi ⁇ mately 0.2 urn, and retrograde peaks at approximately 0.4 and 0.7 ym below the surface of the substrate.
• the spacing between the P + source region 22 was, at its closest approach, approximately 2 ym apart from the P-well 14.
• the current gain of the PNP lateral bipolar parasitic transistor was determined to be approximately 0.1 to 0.2.
• the current gain of the vertical NPN parasitic bipolar transistor was determined to be approximately 2.5. Consequently, the current gain product of the device is between 0.25 and 0.5 approximately and, 04 therefore is by definition inherently immune latch-up.
• CMOS FET structure that is e ssentially immune to latch-up has been described .
• a method of providing the structure and that is applicable to a wide variety of high density CMOS FET fabrication processes characteri zed as a class wherein the essential well region source and drain regions are ion implanted , has also been described .

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• 1983
  • 1983-09-12 US US06/531,546 patent/US4633289A/en not_active Expired - Lifetime
  • 1983-12-12 WO PCT/US1983/001958 patent/WO1985001391A1/en not_active Ceased
  • 1983-12-12 JP JP59500531A patent/JPH0628298B2/ja not_active Expired - Lifetime
  • 1983-12-12 DE DE8484900432T patent/DE3376782D1/de not_active Expired
  • 1983-12-12 EP EP84900432A patent/EP0157779B1/de not_active Expired
• 1984
  • 1984-07-08 IL IL72337A patent/IL72337A/xx not_active IP Right Cessation
  • 1984-09-08 KR KR1019840005516A patent/KR930004343B1/ko not_active Expired - Fee Related

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